公开(公告)号：US09837542B2

公开(公告)日：2017-12-05

申请号：US15104504

申请日：2015-07-17

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Zheng Liu ,  Chunping Long ,  Yu-Cheng Chan ,  Xiaoyong Lu ,  Xialong Li

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/78633 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26513 ,  H01L27/1222 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

摘要： A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

公开(公告)号：US09812536B2

公开(公告)日：2017-11-07

申请号：US15215845

申请日：2016-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L29/08 ,  H01L29/267

CPC分类号： H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

摘要： The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.

公开(公告)号：US09805991B2

公开(公告)日：2017-10-31

申请号：US14830969

申请日：2015-08-20

申请人： International Business Machines Corporation

发明人： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC分类号： H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC分类号： H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US09793414B2

公开(公告)日：2017-10-17

申请号：US15012944

申请日：2016-02-02

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L27/11558 ,  C01G15/00

CPC分类号： H01L29/7869 ,  C01G15/006 ,  C01P2002/77 ,  C01P2002/78 ,  C01P2004/24 ,  C01P2006/10 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02587 ,  H01L21/02592 ,  H01L21/02601 ,  H01L21/02631 ,  H01L27/11558 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969

摘要： To provide a crystalline oxide semiconductor film, an ion is made to collide with a target including a crystalline In—Ga—Zn oxide, thereby separating a flat-plate-like In—Ga—Zn oxide in which a first layer including a gallium atom, a zinc atom, and an oxygen atom, a second layer including an indium atom and an oxygen atom, and a third layer including a gallium atom, a zinc atom, and an oxygen atom are stacked in this order; and the flat-plate-like In—Ga—Zn oxide is irregularly deposited over a substrate while the crystallinity is maintained.

公开(公告)号：US09780124B2

公开(公告)日：2017-10-03

申请号：US15221642

申请日：2016-07-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Yasuyuki Arai

IPC分类号： H01L27/12 ,  H01L27/32 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/30 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1333

CPC分类号： H01L27/124 ,  G02F1/133553 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  G02F2201/123 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02686 ,  H01L21/3003 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L27/3279 ,  H01L29/66537 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78678 ,  H01L29/78684 ,  H01L29/78696

摘要： An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

公开(公告)号：US09773680B1

公开(公告)日：2017-09-26

申请号：US15377503

申请日：2016-12-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Jinping Liu

IPC分类号： H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L27/11

CPC分类号： H01L21/3065 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66553

摘要： Devices and methods of fabricating scaled SRAM with flexible active pitch are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a first portion and a second portion, including a plurality of layers and a patterned mandrel; forming a first set of spacers surrounding the patterned mandrel; etching the dielectric layer; depositing a photoresist layer; opening the photoresist layer over the first portion and not the second portion, removing the patterned mandrel in the open areas; etching the dielectric layer in the open areas; removing the photoresist layer, the remaining patterned mandrels, and the first set of spacers in the first and second portion, etching the silicon layer and MTO layer to form a pattern; forming a second set of spacers around the pattern; and etching a set of fins into the substrate and oxide layer.

公开(公告)号：US20170271502A1

公开(公告)日：2017-09-21

申请号：US15614013

申请日：2017-06-05

申请人： International Business Machines Corporation

发明人： Pouya Hashemi ,  Renee T. Mo ,  John A. Ott ,  Alexander Reznicek

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L29/66 ,  H01L29/161

CPC分类号： H01L29/785 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.

公开(公告)号：US09761448B2

公开(公告)日：2017-09-12

申请号：US14787768

申请日：2015-07-23

申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.

发明人： Liangfen Zhang

IPC分类号： H01L21/02 ,  H01L27/12

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02672 ,  H01L21/02675 ,  H01L27/1229 ,  H01L27/1262 ,  H01L27/1274 ,  H01L27/1281 ,  H01L27/1285

摘要： The present invention provides a method for manufacturing an LTPS TFT substrate structure and a structure of an LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate structure according to the present invention provides patterns of a thermally conductive electrical-insulation layer that are of the same size and regularly distributed under a buffer layer of a driving TFT area to absorb heat in a subsequent excimer laser annealing process so as to speed up the cooling rate of amorphous silicon to form crystal nuclei that gradually grow up in the annealing process. Since the thermally conductive electrical-insulation layer is made up of regularly distributed and size-consistent patterns, crystal grains of a polycrystalline silicon layer located in the driving TFT area show improved consistency and homogeneity and the grain sizes are relatively large to ensure the consistency of electrical property of the driving TFT. The structure of the LTPS TFT substrate structure according to the present invention includes patterns of a thermally conductive electrical-insulation layer that are regularly distributed under a buffer layer of a driving TFT area and have the same size, so that crystal grains of a polycrystalline silicon layer located in the driving TFT area show improved consistency and homogeneity and the grain sizes are relatively large and thus, the electrical property of the driving TFT is consistent.

公开(公告)号：US20170243967A1

公开(公告)日：2017-08-24

申请号：US15519732

申请日：2015-09-24

申请人： INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS

发明人： Daehyun Kim ,  Taejoo Park ,  Yuhang Liu

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L29/24

CPC分类号： H01L29/7786 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/0262 ,  H01L29/0657 ,  H01L29/2206 ,  H01L29/247 ,  H01L29/66969

摘要： An electronic device including a two-dimensional electron gas is provided. The electronic device includes a substrate, a first material layer disposed on the substrate and formed of a binary oxide, a second material layer disposed on the first material layer and formed of a binary oxide, and a two-dimensional electron gas generated between the first material layer and the second material layer.

公开(公告)号：US20170236705A1

公开(公告)日：2017-08-17

申请号：US15518642

申请日：2016-01-22

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Dong LI ,  Xiaoyong LU ,  Xiaolong LI ,  Zheng LIU ,  Shuai ZHANG ,  Yucheng CHAN ,  Chienhung LIU ,  Chunping LONG

IPC分类号： H01L21/02 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L21/0268 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L27/1222 ,  H01L27/1285 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

摘要： The present application provides a low temperature poly-silicon thin film, a low temperature poly-silicon thin film transistor and manufacturing methods thereof, and a display device. The manufacturing method of a low temperature poly-silicon thin film comprises steps of: forming an amorphous silicon thin film on a base; and performing a laser annealing process on the amorphous silicon thin film by using a mask plate to form a low temperature poly-silicon thin film, wherein the mask plate includes a transmissive region and a shielding region surrounding the transmissive region, and two sides of the shielding region adjacent to the transmissive region are in concave-convex shapes. Performance of the low temperature poly-silicon thin film formed by the manufacturing method of a low temperature poly-silicon thin film in the present application is enhanced.