公开(公告)号：US09812536B2

公开(公告)日：2017-11-07

申请号：US15215845

申请日：2016-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L29/08 ,  H01L29/267

CPC分类号： H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

摘要： The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.

公开(公告)号：US20240297076A1

公开(公告)日：2024-09-05

申请号：US18657243

申请日：2024-05-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Chan Yen ,  Ching-Feng Fu ,  Chia-Ying Lee

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002

摘要： An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

公开(公告)号：US12009258B2

公开(公告)日：2024-06-11

申请号：US17227056

申请日：2021-04-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Chan Yen ,  Ching-Feng Fu ,  Chia-Ying Lee

IPC分类号： H01L27/12 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L29/66 ,  H01L23/532 ,  H01L29/165

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

公开(公告)号：US20160329406A1

公开(公告)日：2016-11-10

申请号：US15215845

申请日：2016-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L21/768 ,  H01L29/45 ,  H01L21/311 ,  H01L21/02 ,  H01L21/321 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

摘要： The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.

摘要翻译： 本公开涉及一种具有与晶体管或其它半导体器件的源极/漏极自对准接触的集成芯片的方法。 在一些实施例中，集成芯片具有一对栅极结构，其包括布置在衬底上的栅电极和布置在栅电极上的绝缘材料。 源极/漏极区域布置在该对栅极结构之间的衬底内。 蚀刻停止层沿着该对栅极结构的侧壁并且在源极/漏极区域上方布置，并且电介质层在绝缘材料上方。 源极/漏极触点设置在绝缘材料和蚀刻停止层之上，并且通过蚀刻停止层与一对栅极结构的侧壁分离。 源/漏接触电耦合到源/漏区。

公开(公告)号：US20210225707A1

公开(公告)日：2021-07-22

申请号：US17227056

申请日：2021-04-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Chan Yen ,  Ching-Feng Fu ,  Chia-Ying Lee

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522

摘要： An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

公开(公告)号：US09412656B2

公开(公告)日：2016-08-09

申请号：US14180460

申请日：2014-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC分类号： H01L21/32 ,  H01L21/44 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

摘要： Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact.

摘要翻译： 本公开的一些实施例涉及用于形成与晶体管或其它半导体器件的源极/漏极自对准接触的方法。 该方法包括在衬底上形成一对栅极结构，并且在该对栅极结构之间形成源极/漏极区域。 该方法还包括形成牺牲源极/漏极接触件，该接触件布置在源极/漏极区域之上，并且横向设置在该对栅极结构的相邻侧壁之间。 所述方法还包括形成在所述牺牲源极/漏极接触件上方并在所述一对栅极结构上延伸的介电层。 电介质层与牺牲源极/漏极接触不同。 该方法还包括在牺牲源极/漏极接触件上去除介电层的一部分，随后去除牺牲源极/漏极接触以形成凹陷，并用导电材料填充凹部以形成源极/漏极接触。

公开(公告)号：US20150235897A1

公开(公告)日：2015-08-20

申请号：US14180460

申请日：2014-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L29/40 ,  H01L21/32 ,  H01L21/4757

CPC分类号： H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

摘要： Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact.

摘要翻译： 本公开的一些实施例涉及用于形成与晶体管或其它半导体器件的源极/漏极自对准接触的方法。 该方法包括在衬底上形成一对栅极结构，并且在该对栅极结构之间形成源极/漏极区域。 该方法还包括形成牺牲源极/漏极接触件，该接触件布置在源极/漏极区域之上，并且横向设置在该对栅极结构的相邻侧壁之间。 所述方法还包括形成在所述牺牲源极/漏极接触件上方并在所述一对栅极结构上延伸的介电层。 电介质层与牺牲源极/漏极接触不同。 该方法还包括在牺牲源极/漏极接触件上去除介电层的一部分，随后去除牺牲源极/漏极接触以形成凹陷，并用导电材料填充凹部以形成源极/漏极接触。