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公开(公告)号：US12211859B2
公开(公告)日：2025-01-28
申请号：US17641557
申请日：2021-03-19
Inventor： Chunping Long , Qi Qi , Wanzhi Chen , Xinxin Zhao
Abstract: A light-emitting substrate and a display device. The light-emitting substrate includes a base substrate, an electrode layer and a definition pattern layer; the electrode layer is at a side of the base substrate, and the definition pattern layer is at a side of the electrode layer away from the base substrate; the electrode layer includes a first electrode, and the definition pattern layer covers at least a part of the first electrode; the definition pattern layer includes a plurality of first openings, the plurality of first openings expose a same first electrode. Therefore, the light-emitting substrate can ensure the bonding success rate of the light-emitting substrate, and thus can further improve the product yield of the light-emitting substrate.
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公开(公告)号：US20240272497A1
公开(公告)日：2024-08-15
申请号：US18005421
申请日：2022-03-30
Applicant: BOE Technology Group Co., Ltd.
Inventor： Binbin Tong , Lizhong Wang , Jianbo Xian , Liping Lei , Chunping Long , Yunping Di , Ce Ning
IPC: G02F1/1362 , G02F1/1333 , G02F1/1343
CPC classification number: G02F1/136286 , G02F1/133308 , G02F1/13439
Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.
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公开(公告)号：US11995280B2
公开(公告)日：2024-05-28
申请号：US17436810
申请日：2021-06-08
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chunping Long
IPC: G06F3/044 , G06F3/041 , G09G3/3233
CPC classification number: G06F3/0446 , G06F3/0412 , G06F2203/04112 , G09G3/3233 , G09G2300/0426 , G09G2300/0842
Abstract: A touch structure, a touch display panel and an electronic apparatus are provided. The touch structure includes a first touch electrode extended along a first direction and a second touch electrode extended along a second direction; the first touch electrode includes first electrode main body portions in a first conductive layer (201) and a first connection portion in a second conductive layer (202); the second touch electrode includes second electrode main body portions and a second connection portion in the first conductive layer; the first connection portion is overlapped with the second connection portion in a direction perpendicular to the first conductive layer; the first conductive layer includes first metal meshes formed by first metal lines. The touch structure also includes a dummy electrode in the second conductive layer. The dummy electrode is coupled with at least one of the first connection portion and the second connection portion.
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公开(公告)号：US20210225238A1
公开(公告)日：2021-07-22
申请号：US16769692
申请日：2019-12-09
Inventor： Jianbo Xian , Chunping Long , Hui Li , Yong Qiao
IPC: G09G3/20
Abstract: The present disclosure relates to a driving unit. The driving unit may include a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit may include a plurality of first switching demerits, and at least some of the plurality of first switching elements may be configured to output a first signal to a first output terminal of the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit may include one or more second switching elements, and at least one of the one or more second switching elements may he configured to output a second signal to a second output terminal of the driving unit in response to the control signal from the driving control circuit. The driving control circuit may be configured to output the control signal at a control signal output terminal.
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公开(公告)号：US10510780B2
公开(公告)日：2019-12-17
申请号：US15746687
申请日：2017-07-07
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chunping Long , Pan Li
IPC: H01L27/12 , G02F1/1362 , G02F1/1368 , G02F1/1343
Abstract: An array substrate and a display are provided. The array substrate includes a plurality of sub-pixel regions arranged in rows and columns. The sub-pixel region includes a pixel aperture region. A conductive pattern is provided between two adjacent sub-pixel regions in a row direction, at least part of the conductive pattern being located between pixel aperture regions of the two adjacent sub-pixel regions in the row direction, and the conductive pattern being connected to a common voltage.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10424259B2
公开(公告)日：2019-09-24
申请号：US15526441
申请日：2016-05-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping Long , Yong Qiao
Abstract: Exemplary embodiments of the present disclosure provide a demultiplexer circuit, a signal line circuit and a corresponding output circuit, and a display. The demultiplexer circuit includes at least one first input terminal configured to receive a first signal, at least one second input terminal configured to receive a second signal, at least one first output terminal configured to output the first signal and the second signal, and at least one second output terminal configured to output the first signal and the second signal. The demultiplexer circuit according to exemplary embodiments of the present disclosure can reduce the signal input lines and the input ports, further facilitate to reduce the layout space of wiring.
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公开(公告)号：US10263018B2
公开(公告)日：2019-04-16
申请号：US15718973
申请日：2017-09-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chunping Long
Abstract: Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality of signal lines arranged adjacent to each other at the same layer; and at least one redundant wire at a different layer from the signal lines, wherein each redundant wire corresponds to two adjacent signal lines, and a positive projection of the each redundant wire onto the layer where the signal lines are located covers a part or all of a gap between the two adjacent signal lines corresponding to the each redundant wire.
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公开(公告)号：US10163939B2
公开(公告)日：2018-12-25
申请号：US15552242
申请日：2017-01-09
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping Long , Yong Qiao
IPC: H01L27/12 , H01L29/49 , H01L29/786
Abstract: The present disclosure provides a thin film transistor array substrate and a display device implementing the same. The thin film transistor array substrate includes a substrate; a first signal line formed on the substrate; and a thin film transistor formed on the substrate, and an active layer of the thin film transistor and the first signal line are located on different layers above the substrate and projections of them on a plane where the substrate is located overlap with each other at at least two positions. The present disclosure may improve wiring efficiency and reliability of the thin film transistor array substrate.
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公开(公告)号：US09837542B2
公开(公告)日：2017-12-05
申请号：US15104504
申请日：2015-07-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zheng Liu , Chunping Long , Yu-Cheng Chan , Xiaoyong Lu , Xialong Li
IPC: H01L29/78 , H01L29/66 , H01L27/12 , H01L29/786 , H01L21/02 , H01L21/265
CPC classification number: H01L29/78633 , H01L21/02532 , H01L21/02592 , H01L21/02667 , H01L21/26513 , H01L27/1222 , H01L29/66757 , H01L29/78618 , H01L29/78675 , H01L29/78696
Abstract: A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.
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公开(公告)号：US09748280B2
公开(公告)日：2017-08-29
申请号：US14768009
申请日：2015-01-08
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping Long , Zuqiang Wang
IPC: H01L29/786 , H01L27/12 , G02F1/1368 , H01L29/49 , H01L27/32
CPC classification number: H01L27/1244 , G02F1/1368 , G02F2001/13685 , H01L27/1222 , H01L27/1274 , H01L27/3262 , H01L29/4908 , H01L29/786 , H01L29/78618 , H01L29/78675
Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.
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