公开(公告)号：US20210149261A1

公开(公告)日：2021-05-20

申请号：US16642544

申请日：2019-08-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG

IPC: G02F1/1362 ,  H01L27/12

Abstract: A wiring structure includes a plurality of signal lines on the base substrate, the plurality of signal lines including a plurality of first type signal lines extending in a first direction and a second type signal line extending in a second direction crossing the first direction, the second type signal line being at first ends of the plurality of first type signal lines and spaced from the plurality of first type signal lines, and a plurality of conductive blocks, each of which is between the first ends of two corresponding adjacent signal lines of the plurality of first type signal lines. The plurality of conductive blocks are insulated from the plurality of first type signal lines and electrically connected to the second type signal line.

公开(公告)号：US20210052870A1

公开(公告)日：2021-02-25

申请号：US16831100

申请日：2020-03-26

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yongchun LU ,  Hui LI ,  Pan LI ,  Chunping LONG

IPC: A61M37/00 ,  G03F7/00

Abstract: Embodiments of the present disclosure provide a preparation delivery assembly including: a first substrate, a second substrate, and at least two needles of different lengths, each of which is a hollow needle having a hollow structure; wherein two side walls are provided between the first substrate and the second substrate to define a first chamber for containing a preparation by the first substrate, the second substrate, and the two side walls; at least one first channel that is in communication with the first chamber is provided in the second substrate in a direction substantially perpendicular to the second substrate; and the needles are arranged on a surface of the second substrate distal to the first substrate, and each of the needles is in communication with the first chamber through the at least one first channel to deliver the preparation.

公开(公告)号：US20210027678A1

公开(公告)日：2021-01-28

申请号：US16754953

申请日：2019-09-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping LONG

IPC: G09G3/00 ,  G09G3/20

Abstract: Some embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate includes a test circuit located in a non-display area, wherein the test circuit includes at least one stage of subcircuit, and the subcircuit includes at least one demux; except the first stage of subcircuit, the input ends of the demuxes in the subcircuit are connected with corresponding output ends of the demuxes in the previous stage of subcircuit; except the last stage of subcircuit, the output ends of the demuxes in the subcircuit are connected with corresponding input ends of the demuxes in the next stage of subcircuit; and the input end of the demux in the first stage of subcircuit is connected with a test terminal, and the output ends of the demuxes in the last stage of subcircuit are connected with signal lines in a display area.

公开(公告)号：US20200258937A1

公开(公告)日：2020-08-13

申请号：US16461419

申请日：2018-11-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG

IPC: H01L27/15 ,  H01L33/62 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66

Abstract: An array substrate including a base substrate; a thin film transistor disposed on the base substrate, the thin film transistor including a gate electrode connected to a gate line; an active layer; a gate insulating layer insulating the gate electrode from the active layer; a first electrode connected to a data line; and a second electrode spaced apart from the first electrode; a micro light emitting diode disposed on a side of the gate insulating layer away from the base substrate, the micro light emitting diode including a first electrode, a light emitting layer and a second electrode; and a common electrode. The second electrode of the thin film transistor is connected to one of the first and second electrodes of the micro light emitting diode. The other of the first and second electrodes of the micro light emitting diode is connected to the common electrode.

公开(公告)号：US20200075632A1

公开(公告)日：2020-03-05

申请号：US16462638

申请日：2018-10-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Hui LI ,  Xinyin WU

IPC: H01L27/12 ,  G09G3/00 ,  H01L29/423 ,  H01L29/417 ,  G02F1/1362 ,  G01R31/02 ,  G02F1/1343

Abstract: An array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area surrounding the display area. The array substrate further includes a plurality of signal lines located in the display area, a plurality of test signal lines and a plurality of test control transistors located in the non-display area and respectively corresponding to the plurality of signal lines. Each of the signal lines is connected to a respective one of the test signal lines by a respective one of the test control transistors. The plurality of test control transistors each have a channel width-to-length ratio between 10 and 200.

公开(公告)号：US20180267374A1

公开(公告)日：2018-09-20

申请号：US15807451

申请日：2017-11-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Yongda MA ,  Pan LI

IPC: G02F1/1362 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66

CPC classification number: G02F1/136227 ,  G02F1/134309 ,  G02F1/136213 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/78618

Abstract: An array substrate and a display device are provided, which relate to the field of display and are for alleviating or mitigating the problem of bad contact between the pixel electrode and the drain pad caused by deep via holes. The array substrate includes a plurality of pixel units, each including a drain pad, a pixel electrode and an insulating layer above the drain pad. The drain pad has a first via hole, and the insulating layer has a second via hole that exposes at least a portion of the first via hole and a portion of the drain pad around the first via hole. The pixel electrode extends along an inner wall of the second via hole and contacts the exposed portion of the drain pad.

公开(公告)号：US20180252972A1

公开(公告)日：2018-09-06

申请号：US15561185

申请日：2017-04-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/134363 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/124 ,  H01L27/12 ,  H01L27/124

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes: a plurality of gate lines, a plurality of data lines and a plurality of common electrodes disposed on a base substrate. The plurality of gate lines are extended in a first direction, the plurality of data lines are extended in a second direction. Each of the common electrodes includes an overlap section which overlaps at least one of the data lines in a direction perpendicular to the base substrate. A gap is provided between the overlap sections of two adjacent common electrodes in the second direction, the two adjacent common electrodes overlap the same data lines in the direction perpendicular to the base substrate. An intersection of the data line and the gate line between the two adjacent common electrodes is located within the gap.

公开(公告)号：US20180211975A1

公开(公告)日：2018-07-26

申请号：US15717376

申请日：2017-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping LONG

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L23/52 ,  H01L23/525 ,  H01L27/1248

Abstract: Disclosed are a connection structure, an array substrate, and a display device. A connection structure according to some embodiments of the application includes a connection line, and at least one redundant connection line including a redundant connection section and two connection ends, wherein the redundant connection section partially overlaps with the two connection ends; the connection line is electrically connected with a first signal end and a second signal end; and the connection ends partially overlap respectively with the first signal end and the second signal end. There is at least one redundant connection line between the two signal ends of the connection line, but the redundant connection line is not connected with the two signal ends, and only if the connection line is damaged, then the redundant connection line will be electrically connected with the two signal ends.

公开(公告)号：US20160307978A1

公开(公告)日：2016-10-20

申请号：US14785777

申请日：2015-03-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Xiaoyong LU ,  Xiaolong LI ,  Chien Hung LIU ,  Chunping LONG

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52

CPC classification number: H01L27/3262 ,  H01L27/1248 ,  H01L27/1274 ,  H01L27/1285 ,  H01L27/3246 ,  H01L51/5206 ,  H01L51/5221 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/558

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.

Abstract translation: 提供阵列基板，阵列基板和显示装置的制造方法。 阵列基板的制造方法包括：在基底（1）上形成第一导电薄膜（100）; 以及图案化所述第一导电薄膜（100），以在所述基底基板（1）的第一区域（11）上形成阴极（11）的图案，并在第二导电薄膜（1）上形成栅电极（4）的图案 基底（1）的区域（12）。 可以减少阵列基板的制造工艺的复杂性和处理时间，通过形成发光二极管和栅电极的阴极层，可以简化有机电致发光面板的制造工艺，并且可以降低生产成本 通过一个图案化工艺同时在基底基板的不同区域中的薄膜晶体管层。

公开(公告)号：US20160254389A1

公开(公告)日：2016-09-01

申请号：US14768349

申请日：2015-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong LU ,  Zheng LIU ,  Liang SUN ,  Xiaolong LI ,  Chunping LONG

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L27/12

CPC classification number: H01L29/78618 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/1222 ,  H01L27/1274 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

Abstract: A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S1: sequentially forming an active layer (3), a gate insulation layer (4), a gate electrode (5) and an interlayer insulation layer (6) on a base substrate (1); S2: forming a first metal thin film layer (8); S3: performing a hydrogenation treatment on the active layer (3) and the gate insulation layer (6); S4: forming a second metal thin film layer (7), the second metal thin film layer (7) being used for forming a source electrode and a drain electrode.

Abstract translation: 提供一种低温多晶硅薄膜晶体管及其制造方法，阵列基板和显示装置。 该方法包括：S1：在基底（1）上依次形成有源层（3），栅极绝缘层（4），栅电极（5）和层间绝缘层（6）; S2：形成第一金属薄膜层（8）; S3：在有源层（3）和栅极绝缘层（6）上进行氢化处理; S4：形成第二金属薄膜层（7），第二金属薄膜层（7）用于形成源电极和漏电极。