公开(公告)号：US3524992A

公开(公告)日：1970-08-18

申请号：US3524992D

申请日：1967-08-17

申请人： SYLVANIA ELECTRIC PROD

发明人： KARDASH JOHN J

IPC分类号： H03K19/08 ,  H03K19/088 ,  H03K19/36

CPC分类号： H03K19/08 ,  H03K19/088

公开(公告)号：US3011075A

公开(公告)日：1961-11-28

申请号：US81735159

申请日：1959-06-01

申请人： DEVELOPMENTS LTD COMP

发明人： BERNARD TOMLINSON TERENCE

IPC分类号： H03K19/08

CPC分类号： H03K19/08

公开(公告)号：US20190199338A1

公开(公告)日：2019-06-27

申请号：US16221855

申请日：2018-12-17

申请人： STMicroelectronics S.r.l.

发明人： Marco ZAMPROGNO ,  Alireza TAJFAR

IPC分类号： H03K17/041 ,  H03K17/687 ,  H03M1/06

CPC分类号： H03K17/04106 ,  G03B21/2033 ,  H03K17/08122 ,  H03K17/6871 ,  H03K19/08 ,  H03M1/06 ,  H03M1/66

摘要： A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

公开(公告)号：US20190098759A1

公开(公告)日：2019-03-28

申请号：US16135982

申请日：2018-09-19

申请人： Nthdegree Technologies Worldwide Inc.

发明人： Richard Austin Blanchard ,  William Johnstone Ray

IPC分类号： H05K1/16 ,  H01L29/06 ,  H05K1/02 ,  H01L21/77 ,  H01L21/02 ,  H05K3/12 ,  H01L29/40

CPC分类号： H05K1/16 ,  H01L21/02288 ,  H01L21/561 ,  H01L21/77 ,  H01L22/22 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L29/0646 ,  H01L29/401 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/8284 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95146 ,  H01L2224/97 ,  H03K19/017581 ,  H03K19/08 ,  H05K1/0293 ,  H05K1/189 ,  H05K3/12 ,  H05K3/30 ,  H05K2201/026 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2203/0783 ,  H05K2203/1115 ,  H05K2203/175 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00014

摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.

公开(公告)号：US10084435B2

公开(公告)日：2018-09-25

申请号：US15706445

申请日：2017-09-15

申请人： Adam Watkins ,  Spyros Tragoudas

发明人： Adam Watkins ,  Spyros Tragoudas

IPC分类号： H03K3/037 ,  H03K19/08

CPC分类号： H03K3/0375 ,  H03K19/08 ,  H03K19/20

摘要： Disclosed are a latch circuit and method for preventing double node upsets (DNUs). A first, second, and third storage circuit, each comprising four inputs and an output, are electrically interconnected with a first and second three-input c-element circuit, each comprising three inputs and an output, and a two-input c-element circuit comprising two inputs and an output. The output of the first storage circuit is connected to a first input of the first three-input c-element circuit, a first input of the third storage circuit and a third input of the second storage circuit. The output of the second storage circuit is connected to a second input of the first three-input c-element circuit, a first input of the two-input c-element circuit, and a second input of the second three-input c-element circuit. The output of the third storage circuit is connected to a second input of the two-input c-element circuit, a third input of the first three-input c-element circuit and a third input of the second three-input c-element circuit.

公开(公告)号：US20170358254A1

公开(公告)日：2017-12-14

申请号：US15615997

申请日：2017-06-07

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tatsunori INOUE ,  Takeshi AOKI

IPC分类号： G09G3/20 ,  G09G3/36 ,  H01L27/12 ,  G09G3/3225 ,  H03K19/08

CPC分类号： G09G3/2007 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/046 ,  G09G2300/0814 ,  G09G2300/0833 ,  G09G2310/027 ,  G09G2360/144 ,  H01L27/1225 ,  H03K19/08

摘要： An object is to provide a semiconductor device that automatically adjusts the luminance of a display device. The semiconductor device includes an illuminometer, a threshold detector, a timing controller, a digital-to-analog converter circuit, a first display panel, and a second display panel. The illuminance of external light is measured with the illuminometer, and the threshold value of digital video data is determined by the threshold detector in accordance with the illuminance. The timing controller generates a signal for the first display panel or a signal for the second display panel on the basis of the threshold value and video data transmitted from the outside. The signal for the first display panel and the signal for the second display panel are input to one digital-to-analog converter circuit and converted into digital signals, and the obtained digital signals are input to a corresponding one of the first display panel and the second display panel.

公开(公告)号：US09843328B1

公开(公告)日：2017-12-12

申请号：US15173507

申请日：2016-06-03

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/017 ,  H03K19/177 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H03K19/1774 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H03K17/223 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/17708

摘要： A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

公开(公告)号：US09754955B2

公开(公告)日：2017-09-05

申请号：US14983682

申请日：2015-12-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Cheng Wu ,  I-Ching Chen

IPC分类号： H01L21/28 ,  H01L21/31 ,  H01L27/1157 ,  H03K19/08 ,  H01L27/11573 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/51

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32133 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833 ,  H03K19/08

摘要： An integrated circuit (IC) using high-κ metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high κ dielectric layers. A high-κ-last method for manufacturing the IC is also provided.

公开(公告)号：US09741931B1

公开(公告)日：2017-08-22

申请号：US15404940

申请日：2017-01-12

申请人： SK hynix Inc.

发明人： Hong Jung Kim ,  Young Hee Yoon ,  Jeong Ho Yi

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L45/141 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/52 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1683 ,  H03K19/08

摘要： A semiconductor integrated circuit device may include a first signal line, a second signal line, a variable resistance material layer, and a third signal line. The second signal line may be positioned coplanar with the first signal line. The second signal line may be parallel to the first signal line. The variable resistance material layer may include a horizontal region arranged on the first and second signal lines, and may include a vertical region extending upwardly from an end of the horizontal region. The third signal line may be positioned on a plane different from a plane on which the first and second signal lines may be positioned. The third signal line may be arranged on an end of the vertical region of the variable resistance material layer.

公开(公告)号：US09197215B1

公开(公告)日：2015-11-24

申请号：US14268765

申请日：2014-05-02

申请人： The Regents of the University of California

发明人： Alexander A. Balandin ,  Alexander Khitun ,  Roger Lake

IPC分类号： H01L29/06 ,  H03K19/08 ,  H01L47/00 ,  H01L29/16 ,  H01L29/786 ,  H03K19/20 ,  B82Y99/00

CPC分类号： H01L29/16 ,  B82Y99/00 ,  H01L29/1606 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/78684 ,  H01L47/00 ,  H03K5/19 ,  H03K19/08 ,  H03K19/20 ,  Y10S977/936

摘要： A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits.

摘要翻译： 公开了具有负差分电阻（NDR）区域的双栅晶体管。 双栅极晶体管包括背栅极，设置在背栅极上的零带隙石墨烯层，设置在与顶栅极相邻的零带隙石墨烯层的一部分上的顶栅极，以及排列的漏极 在与顶栅相邻并且从源极位移的零带隙石墨烯层的一部分上。 还包括动态偏置控制器，其被配置为同时扫描跨越Dirac点的源极 - 漏极电压和顶栅极电压，以在NDR区域内提供操作。 采用NDR区域内的操作来实现非布尔逻辑功能。 基于石墨烯的非布尔逻辑电路由所公开的双栅极晶体管的多个构成。 也通过基于石墨烯的非布尔逻辑电路公开了在100 GHz和500 GHz之间运行的模式识别电路。