公开(公告)号：US4897705A

公开(公告)日：1990-01-30

申请号：US328799

申请日：1989-03-23

Applicant: Takatsugu Kitora ,  Youichirou Taki

Inventor： Takatsugu Kitora ,  Youichirou Taki

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/735 ,  H03K19/088

CPC classification number: H01L29/735 ,  H03K19/088

Abstract: A semiconductor integrated circuit device comprises a lateral pnp transistor having a base to which an input signal is applied and a first npn transistor having a base to which a potential appearing at the emitter of the pnp transistor is applied, which transistors constitute a bipolar logic circuit. In the circuit device, the width of the base of the pnp transistor is determined to be in the range of from 5 .mu.m to 7 .mu.m.

Abstract translation: 半导体集成电路器件包括具有施加输入信号的基极的横向pnp晶体管和具有施加在pnp晶体管的发射极处出现的电位的基极的第一npn晶体管，该晶体管构成双极逻辑电路 。 在电路装置中，pnp晶体管的基极的宽度被确定在5μm到7μm的范围内。

公开(公告)号：US4896058A

公开(公告)日：1990-01-23

申请号：US186502

申请日：1988-04-26

Applicant: Robert J. Murray

Inventor： Robert J. Murray

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/088

CPC classification number: H03K19/00353 ,  H03K19/088

Abstract: In conventional logic buffer circuits, internal signal overshoot during switching transitions causes power supply spikes or bounce, which may in turn degrade the operational reliability of other circuits in the same system. By using a pair of current amplifier circuits within the logic buffer circuit to shunt a portion of the signal overshoot, the output current of the logic buffer circuit is caused to change linearly with time, so that power supply bounce or spikes are substantially reduced.

公开(公告)号：US4704548A

公开(公告)日：1987-11-03

申请号：US697303

申请日：1985-01-31

Applicant: Bobby D. Strong ,  Robert C. Martin ,  Kevin M. Ovens ,  James F. Salzman

Inventor： Bobby D. Strong ,  Robert C. Martin ,  Kevin M. Ovens ,  James F. Salzman

IPC: H03K19/0175 ,  H03K19/013 ,  H03K19/082 ,  H03K19/088 ,  H03K19/01 ,  H03K17/04 ,  H03K17/60

CPC classification number: H03K19/088 ,  H03K19/0136 ,  H03K19/0826

Abstract: The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).

Abstract translation: 本说明书公开了一种输入晶体管（14），其响应于端子10处的输入电压跃迁而在高阻抗状态和低阻抗状态之间是可变的。输出晶体管（16）耦合到输入晶体管（14）并响应于输入转换 在端子10处用于改变阻抗状态。 包括加速晶体管（44）的电路耦合在输入晶体管（14）和输出晶体管（16）之间，用于向输出晶体管（16）施加相加的电流以加速阻抗状态的改变。 电路对输出晶体管（16）施加相加的电流，直到端子（18）的输出电压下降到输出晶体管（16）的基极 - 发射极电压的两倍以下。

公开(公告)号：US4675548A

公开(公告)日：1987-06-23

申请号：US670103

申请日：1984-11-13

Applicant: Kevin S. Eshbaugh

Inventor： Kevin S. Eshbaugh

IPC: H03K19/013 ,  H03K19/088 ,  H03K17/04 ,  H03K5/08

CPC classification number: H03K19/088 ,  H03K19/013

Abstract: A transistor-transistor logic gate circuit arrangement for saturation control while providing TTL input and output compatibility. The circuit comprises a resistor divider network coupled across the base emitter junction of a phase splitter transistor. A preselected fraction of the phase splitter's V.sub.BE is produced at the base of an antisaturation transistor. The antisaturation transistor is coupled across the collector-base of an output transistor thereby providing a method of clamping an output transistor using V.sub.BE as a reference voltage. Because V.sub.BE is used as the reference, the circuit can maintain TTL output voltage levels while preventing the output transistor from saturating in an extremely wide range of operating temperatures.

Abstract translation: 晶体管晶体管逻辑门电路布置，用于饱和控制，同时提供TTL输入和输出兼容性。 电路包括耦合在分相器晶体管的基极发射极结上的电阻分压器网络。 分相器VBE的预选部分在抗饱和晶体管的基极处产生。 该抗饱和晶体管耦合在输出晶体管的集电极基极上，从而提供了一种使用VBE作为参考电压来钳位输出晶体管的方法。 由于使用VBE作为参考，电路可以保持TTL输出电压电平，同时防止输出晶体管在极宽的工作温度范围内饱和。

公开(公告)号：US4634898A

公开(公告)日：1987-01-06

申请号：US554474

申请日：1983-11-22

Applicant: Gary Gouldsberry ,  Albert Chan ,  Cyrus Tsui ,  Mark Fitzpatrick

Inventor： Gary Gouldsberry ,  Albert Chan ,  Cyrus Tsui ,  Mark Fitzpatrick

IPC: H03K19/013 ,  H03K19/088 ,  H03K17/04 ,  H03K17/60

CPC classification number: H03K19/013 ,  H03K19/0136 ,  H03K19/088

Abstract: A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

Abstract translation: 独特的双反相缓冲器具有第一装置，用于反转和隔离数字输入信号，第二装置重新转换并进一步隔离输入信号，以及包括输出晶体管94的输出装置。双反相缓冲器配置有主动上拉电阻， 输出晶体管92的下降装置。通过双重反转缓冲器的高到低的传播延迟时间和低到高的传播延迟时间通过使用有源下拉装置而减少。 输出晶体管的快速关断是通过将晶体管耦合到其基极来实时地将其截止的。 在优选实施例中，钳位电路201用于将输出电压保持在最大预定电平，以进一步减少将输出电压降低到逻辑“0”状态所花费的时间。

公开(公告)号：US4585953A

公开(公告)日：1986-04-29

申请号：US515419

申请日：1983-07-20

Applicant: Gene J. Gaudenzi ,  John P. Norsworthy ,  Nghia V. Phan ,  Dennis C. Reedy

Inventor： Gene J. Gaudenzi ,  John P. Norsworthy ,  Nghia V. Phan ,  Dennis C. Reedy

IPC: H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/615 ,  H03K19/088

CPC classification number: H03K5/02 ,  H03K19/088

Abstract: Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

Abstract translation: 通过利用选择性地切换晶体管来放电输出下拉晶体管的基极，并且通过在基极电流路径中使用达林顿上拉的第一级的大电阻来减小片外驱动电路中的功耗 晶体管。 具有较大发射极面积并耦合到较低电位源的附加晶体管与正常分相晶体管并联连接，以提供额外的输出电流吸收能力，并且连接电流镜以控制通过相分离晶体管 以及用于控制下拉输出晶体管的导通转变的附加晶体管。

公开(公告)号：US4521700A

公开(公告)日：1985-06-04

申请号：US452541

申请日：1982-12-23

Applicant: Richard J. Blumberg ,  Stewart Brenner ,  Rocco J. Robortaccio

Inventor： Richard J. Blumberg ,  Stewart Brenner ,  Rocco J. Robortaccio

IPC: H03K19/013 ,  H03K19/088 ,  H03K19/003

CPC classification number: H03K19/088 ,  H03K19/013

Abstract: Disclosed is the addition of passive feedback to a prior art T.sup.2 L circuit. The T.sup.2 L circuit with feedback, in accordance with the invention, has a lower power dissipation while retaining noise immunity and small gate delay. The additional resistor required for the feedback T.sup.2 L circuit, in accordance with the invention, can be incorporated into the T.sup.2 L cell without increasing the cell size. The feedback T.sup.2 L circuit, in accordance with the invention, lends itself to the addition of an integrated direct-coupled inverter (DCI) function. The feedback T.sup.2 L circuit, in accordance with the invention, permits more function to be placed on an integrated circuit semiconductor chip while maintaining gate performance and adherence to power restrictions.

Abstract translation: 公开了向现有技术的T2L电路添加无源反馈。 根据本发明的具有反馈的T2L电路具有较低的功率消耗，同时保持抗噪声性和小的门延迟。 根据本发明，反馈T2L电路所需的附加电阻可以并入T2L电池中而不增加电池尺寸。 根据本发明的反馈T2L电路适用于添加集成的直接耦合逆变器（DCI）功能。 根据本发明的反馈T2L电路允许将更多的功能放置在集成电路半导体芯片上，同时保持门性能并遵守功率限制。

公开(公告)号：US4413194A

公开(公告)日：1983-11-01

申请号：US282116

申请日：1981-07-10

Applicant: William A. Birch

Inventor： William A. Birch

IPC: H03K19/003 ,  H03K19/088 ,  H03K19/084

CPC classification number: H03K19/00307 ,  H03K19/088

Abstract: A transistor-transistor logic circuit includes an output stage comprising a pull-up and pull-down transistor and an input stage for receiving one or more binary logic signals. First and second current drive transistors regulate base drive to the pull-up and pull-down transistors respectively. A first switching transistor turns said first current drive transistor off when the binary signals reach a first logic level. A second switching transistor turns the second current drive transistor on when the binary logic signals reach the first logic level. In this manner, negative reflections at the output of the circuit will not result in the pull-up transistor and its associated current drive transistor being turned off.

Abstract translation: 晶体管晶体管逻辑电路包括具有上拉和下拉晶体管的输出级和用于接收一个或多个二进制逻辑信号的输入级。 第一和第二电流驱动晶体管分别将基极驱动调节到上拉和下拉晶体管。 当二进制信号达到第一逻辑电平时，第一开关晶体管关断所述第一电流驱动晶体管。 当二进制逻辑信号达到第一逻辑电平时，第二开关晶体管导通第二电流驱动晶体管导通。 以这种方式，电路输出端的负反射不会导致上拉晶体管及其相关联的电流驱动晶体管截止。

公开(公告)号：US4311927A

公开(公告)日：1982-01-19

申请号：US58674

申请日：1979-07-18

Applicant: David A. Ferris

Inventor： David A. Ferris

IPC: H03K19/0175 ,  H03K19/018 ,  H03K19/082 ,  H03K19/088

CPC classification number: H03K19/088 ,  H03K19/0826

Abstract: A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used. For passive element discharge of Miller current a low forward impedance high backward impedance large surface area diode is used.

Abstract translation: 晶体管逻辑三态输出门或器件设置有一方面在一方面的使能栅极和下拉元件晶体管的基极之间耦合的有源或无源元件布置。 当使能栅极处于低电位并且输出器件处于高阻抗第三状态时，该耦合提供从下拉元件的基极到地电位或低电位的低阻抗路径。 因此，下拉元件晶体管的基极处的米勒反馈电流被转移到地。 耦合装置在相反方向上提供高阻抗电流，从而当使能栅极处于高电位时阻断来自使能栅极的电流。 对于米勒电流的有源放电，在使能栅极和下拉元件之间的双反相串联耦合中提供了三个晶体管。 可替代地，使用多发射极结晶体管。 对于毫米电流的无源元件放电，使用低正向阻抗高反向阻抗大表面积二极管。

公开(公告)号：US4045689A

公开(公告)日：1977-08-30

申请号：US691934

申请日：1976-06-01

Applicant: Gary W. Tietz

Inventor： Gary W. Tietz

IPC: H03K19/013 ,  H03K19/088 ,  H03K19/34

CPC classification number: H03K19/013 ,  H03K19/088

Abstract: A TTL gate circuit is provided with an additional transistor biased by the base of the input transistor. This additional transistor supplies current to the phase splitter emitter load, to thereby bias the phase splitter transistor off until the input voltage is high enough to turn both the phase splitter transistor and the output transistor on. The result is a substantially square voltage transfer characteristic.