公开(公告)号：US20180012974A1

公开(公告)日：2018-01-11

申请号：US15527105

申请日：2015-11-13

申请人： ROHM CO., LTD.

发明人： Yuki NAKANO ,  Ryota NAKAMURA

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/04 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7813

摘要： A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region.

公开(公告)号：US09859416B2

公开(公告)日：2018-01-02

申请号：US15172264

申请日：2016-06-03

申请人： Renesas Electronics Corporation

发明人： Takahiro Mori ,  Hiroki Fujii

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40

CPC分类号： H01L29/7823 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/311 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

摘要： An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor.In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

公开(公告)号：US09859372B2

公开(公告)日：2018-01-02

申请号：US14988507

申请日：2016-01-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Li Liu ,  Xianyong Pu ,  Guangli Yang ,  Gangning Wang ,  ChiChung Tai ,  Hong Sun

IPC分类号： H01L21/761 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/0847 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.

公开(公告)号：US20170352757A1

公开(公告)日：2017-12-07

申请号：US15613707

申请日：2017-06-05

申请人： Alfred I. Grayzel

发明人： Alfred I. Grayzel

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/10 ,  H01L29/812 ,  H01L29/808

CPC分类号： H01L29/7831 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/8124

摘要： A Field Effect Transistor including: a channel with one end designated the source and the other end designated the drain; a means for connecting to said source end of said channel; a means for connecting to said drain end of said channel; a gate divided into a plurality of segments each insulated from one another; a means for adjusting the bias of each of said segments independently of one another, whereby the depletion region in said channel can be adjusted to avoid pinch-off and to maximize the efficiency of said Field Effect Transistor.

公开(公告)号：US09818542B2

公开(公告)日：2017-11-14

申请号：US14882800

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L21/8234 ,  H01G4/30 ,  B29C37/00 ,  B29C47/06 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/33 ,  B29C47/56 ,  B32B27/00 ,  B32B7/02 ,  B32B27/08 ,  B32B27/28 ,  B32B27/30 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B3/08 ,  B29K23/00 ,  B29K105/16 ,  B29K507/04 ,  B29L9/00 ,  B29L31/34

CPC分类号： H01L29/7856 ,  B29C37/0025 ,  B29C47/065 ,  B29C47/56 ,  B29K2023/12 ,  B29K2105/16 ,  B29K2507/04 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2009/003 ,  B29L2009/005 ,  B29L2031/34 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B2262/106 ,  B32B2264/105 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2274/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/518 ,  B32B2307/732 ,  B32B2457/16 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7851 ,  H01L2029/7858

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US20170229575A1

公开(公告)日：2017-08-10

申请号：US15017197

申请日：2016-02-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHEN-LIANG CHU ,  TA-YUAN KUNG ,  KER-HSIAO HUO ,  YI-HUAN CHEN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L29/06

CPC分类号： H01L29/7836 ,  H01L23/5226 ,  H01L29/0615 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

公开(公告)号：US09711621B2

公开(公告)日：2017-07-18

申请号：US14446741

申请日：2014-07-30

申请人： Infineon Technologies AG

发明人： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

摘要： A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.

公开(公告)号：US20170194315A1

公开(公告)日：2017-07-06

申请号：US15464362

申请日：2017-03-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L27/0277 ,  H01L27/0259 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

摘要： An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.

公开(公告)号：US20170194206A1

公开(公告)日：2017-07-06

申请号：US15467123

申请日：2017-03-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li ,  Chun-Chen Yeh

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/10 ,  H01L29/78 ,  H01L21/306 ,  H01L21/324

CPC分类号： H01L21/823412 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

公开(公告)号：US20170186865A1

公开(公告)日：2017-06-29

申请号：US15458793

申请日：2017-03-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.