公开(公告)号：US20230395436A1

公开(公告)日：2023-12-07

申请号：US17834202

申请日：2022-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yuan Wu ,  Ka-Hing Fung ,  Min Jiao ,  Da-Wen Lin ,  Wei-Yuan Jheng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L21/823892 ,  H01L27/0928 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66742

Abstract: Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.

公开(公告)号：US09768256B2

公开(公告)日：2017-09-19

申请号：US15076061

申请日：2016-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US09373704B2

公开(公告)日：2016-06-21

申请号：US14552237

申请日：2014-11-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

公开(公告)号：US09105664B2

公开(公告)日：2015-08-11

申请号：US14279689

申请日：2014-05-16

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Abstract translation: 一种装置包括具有应变通道区的衬底，沟道区上的电介质层，介电层上的第一和第二导电层具有第一值的特性，以及具有特征的导电层之间的应变诱发导电层 具有与第一值不同的第二值。 不同的方面涉及一种装置，其包括衬底，从衬底延伸的第一和第二突起，第一突起具有拉伸应变的第一沟道区，第二突起具有压缩应变的第二沟道区，以及第一和第二栅结构 分别接合第一和第二突起。 第一栅极结构包括电介质层，电介质层上的第一和第二导电层，以及在导电层之间的应变感应导电层。 第二栅极结构包括与第二沟道区相邻的高k电介质层和金属层。

公开(公告)号：US20150111361A1

公开(公告)日：2015-04-23

申请号：US14586013

申请日：2014-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

IPC: H01L49/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823437 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/8605

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括提供包括隔离区域的衬底，在隔离区域上形成电阻器，以及在电阻器上形成接触。 该方法还包括以在电阻器的深度处逐步增加的掺杂剂浓度进行注入，并且随着深度增加而保持基本恒定。

公开(公告)号：US08951875B2

公开(公告)日：2015-02-10

申请号：US13710078

申请日：2012-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures.

Abstract translation: 半导体结构包括衬底，栅极结构和两个含硅结构。 衬底包括限定在其中的两个凹槽和第一掺杂剂类型的两个掺杂区域。 两个掺杂区域中的每一个沿着底表面和两个凹槽中对应的一个的侧壁的至少一部分延伸。 栅极结构在衬底上并且在两个凹部之间。 两个含硅结构体是与第一掺杂剂类型不同的第二掺杂剂型。 两个含硅结构中的每一个填充两个凹部中的相应的一个，并且两个含硅结构中的每一个的上部的掺杂浓度高于两个含硅结构中的每一个的下部的掺杂浓度 。

公开(公告)号：US20140248751A1

公开(公告)日：2014-09-04

申请号：US14279689

申请日：2014-05-16

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Abstract translation: 一种装置包括具有应变通道区的衬底，沟道区上的电介质层，介电层上的第一和第二导电层具有第一值的特性，以及具有特征的导电层之间的应变诱发导电层 具有与第一值不同的第二值。 不同的方面涉及一种装置，其包括衬底，从衬底延伸的第一和第二突起，第一突起具有拉伸应变的第一沟道区，第二突起具有压缩应变的第二沟道区，以及第一和第二栅结构 分别接合第一和第二突起。 第一栅极结构包括电介质层，电介质层上的第一和第二导电层，以及在导电层之间的应变感应导电层。 第二栅极结构包括与第二沟道区相邻的高k电介质层和金属层。

公开(公告)号：US20130230958A1

公开(公告)日：2013-09-05

申请号：US13863963

申请日：2013-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.