公开(公告)号：US12255230B2

公开(公告)日：2025-03-18

申请号：US17709583

申请日：2022-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Lin Lee ,  Choh-Fei Yeap ,  Da-Wen Lin ,  Chih-Chieh Yeh

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

公开(公告)号：US12057506B2

公开(公告)日：2024-08-06

申请号：US17370543

申请日：2021-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ming Hsu ,  Da-Wen Lin ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/762 ,  H01L29/41791 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

公开(公告)号：US20190115428A1

公开(公告)日：2019-04-18

申请号：US16210305

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/32 ,  H01L29/04 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856 ,  H05K999/99

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US20180006117A1

公开(公告)日：2018-01-04

申请号：US15707886

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/417 ,  H01L29/32 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US09590101B2

公开(公告)日：2017-03-07

申请号：US15161723

申请日：2016-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsiang Huang ,  Da-Wen Lin

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method comprises forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench, applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process, depositing a first tensile film layer on sidewalls and a bottom of the trench, converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process and forming an isolation region over the first dislocation plane.

Abstract translation: 一种方法包括在衬底上形成第一鳍片和第二鳍片，其中所述第一鳍片和所述第二鳍片由沟槽分开，对所述衬底施加第一预非晶注入（PAI）工艺并形成第一PAI区域的底层 作为第一PAI工艺的结果的沟槽，在沟槽的侧壁和底部上沉积第一拉伸膜层，使用第一退火工艺将第一PAI区域转换成沟槽下面的第一位错平面，并形成隔离区域 第一位错平面。

公开(公告)号：US09293534B2

公开(公告)日：2016-03-22

申请号：US14222401

申请日：2014-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract translation: 提供了在finFET器件的源极和漏极区域中形成位错的机构的实施例。 这些机构涉及凹陷翅片并去除隔离结构相邻鳍片中的电介质材料，以增加位错形成的外延区域。 这些机制还涉及在凹入的源极和漏极区域中的外延生长之前或之后进行预非晶注入（PAI）工艺。 在PAI工艺之后的退火工艺可以实现源极和漏极区域中位错的一致生长。 源极和漏极区域（或应力区域）中的位错可以一致地形成，以在源极和漏极区域中产生靶向应变，以改善NMOS器件的载流子迁移率和器件性能。

公开(公告)号：US09281356B2

公开(公告)日：2016-03-08

申请号：US14586013

申请日：2014-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/8605 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823437 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/8605

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括提供包括隔离区域的衬底，在隔离区域上形成电阻器，以及在电阻器上形成接触。 该方法还包括以在电阻器的深度处逐步增加的掺杂剂浓度进行注入，并且随着深度增加而保持基本恒定。

公开(公告)号：US08703593B2

公开(公告)日：2014-04-22

申请号：US13918682

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/336 ,  H01L21/225 ,  H01L21/385

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

公开(公告)号：US12040383B2

公开(公告)日：2024-07-16

申请号：US17465762

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Lin Lee ,  Choh Fei Yeap ,  Da-Wen Lin ,  Chih-Chieh Yeh

IPC: H01L29/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/0259 ,  H01L21/28123 ,  H01L21/764 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78621 ,  H01L29/78696

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

公开(公告)号：US11916151B2

公开(公告)日：2024-02-27

申请号：US17357997

申请日：2021-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Ming Hsu ,  Yi-Jing Li ,  Chih-Hsin Ko ,  Kuang-Hsin Chen ,  Da-Wen Lin ,  Clement Hsingjen Wann

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.