公开(公告)号：US12057506B2

公开(公告)日：2024-08-06

申请号：US17370543

申请日：2021-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ming Hsu ,  Da-Wen Lin ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/762 ,  H01L29/41791 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

公开(公告)号：US11942467B2

公开(公告)日：2024-03-26

申请号：US17351240

申请日：2021-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Sheng Chen ,  Yi-Jing Li ,  Chia-Ming Hsu ,  Wan-Lin Tsai ,  Clement Hsingjen Wann

IPC: H01L23/64 ,  H01L21/70 ,  H01L27/01 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L21/707 ,  H01L28/60

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

公开(公告)号：US11784183B2

公开(公告)日：2023-10-10

申请号：US18084292

申请日：2022-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Tang Lin ,  Clement Hsingjen Wann ,  Neng-Kuo Chen

IPC: H01L27/06 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L27/0688 ,  H01L23/522 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

公开(公告)号：US20230060423A1

公开(公告)日：2023-03-02

申请号：US17986119

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： You-Ru Lin ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08

Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.

公开(公告)号：US11508627B2

公开(公告)日：2022-11-22

申请号：US17067193

申请日：2020-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yi-Jing Lee ,  Ya-Yun Cheng ,  Hau-Yu Lin ,  I-Sheng Chen ,  Chia-Ming Hsu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

公开(公告)号：US11450571B2

公开(公告)日：2022-09-20

申请号：US16404540

申请日：2019-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Ching-Hua Lee ,  Chung-Cheng Wu ,  Clement Hsingjen Wann

IPC: H01L21/8238 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L27/092

Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

公开(公告)号：US11362000B2

公开(公告)日：2022-06-14

申请号：US16865049

申请日：2020-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

公开(公告)号：US20210036131A1

公开(公告)日：2021-02-04

申请号：US17063459

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： You-Ru Lin ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08

Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.

公开(公告)号：US20200258784A1

公开(公告)日：2020-08-13

申请号：US16865049

申请日：2020-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/8238

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

公开(公告)号：US10734411B2

公开(公告)日：2020-08-04

申请号：US16051280

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Tang Lin ,  Chun-Hsiung Tsai ,  Clement Hsingjen Wann

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/10 ,  H01L21/84 ,  H01L29/165

Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.