公开(公告)号：US12230713B2

公开(公告)日：2025-02-18

申请号：US17410048

申请日：2021-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Wei Chen ,  Chi-Sheng Lai ,  Shih-Hao Lin ,  Jian-Hao Chen ,  Kuo-Feng Yu

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

公开(公告)号：US20240413221A1

公开(公告)日：2024-12-12

申请号：US18770408

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Chih-Yu Hsu ,  Hui-Chi Chen ,  Shan-Mei Liao ,  Jian-Hao Chen ,  Cheng-Hao Hou ,  Huang-Chin Chen ,  Cheng Hong Yang ,  Shih-Hao Lin ,  Tsung-Da Lin ,  Da-Yuan Lee ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Chi On Chui ,  Yen-Ming Chen

IPC: H01L29/423 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/417 ,  H01L29/51 ,  H01L29/786

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

公开(公告)号：US12119389B2

公开(公告)日：2024-10-15

申请号：US18360854

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu ,  Yu-Ming Lin ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66795 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/76224 ,  H01L29/665

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

公开(公告)号：US20240332382A1

公开(公告)日：2024-10-03

申请号：US18738303

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsiang Chan ,  Shan-Mei Liao ,  Wen-Hung Huang ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

公开(公告)号：US11972982B2

公开(公告)日：2024-04-30

申请号：US17865311

申请日：2022-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hsiung Tsai ,  Yu-Ming Lin ,  Kuo-Feng Yu ,  Ming-Hsi Yeh ,  Shahaji B. More ,  Chandrashekhar Prakash Savant ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L21/82 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/02057 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

公开(公告)号：US20230063857A1

公开(公告)日：2023-03-02

申请号：US17461499

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Chih-Yu Hsu ,  Hui-Chi Chen ,  Shan-Mei Liao ,  Jian-Hao Chen ,  Cheng-Hao Hou ,  Huang-Chin Chen ,  Cheng Hong Yang ,  Shih-Hao Lin ,  Tsung-Da Lin ,  Da-Yuan Lee ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Chi On Chui ,  Yen-Ming Chen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/51 ,  H01L29/417 ,  H01L21/3105 ,  H01L29/40

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

公开(公告)号：US20230010952A1

公开(公告)日：2023-01-12

申请号：US17737851

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Yen-Ju Chen ,  Chun-Chih Cheng

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

公开(公告)号：US20220336609A1

公开(公告)日：2022-10-20

申请号：US17233098

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsiang Chan ,  Wen-Hung Huang ,  Shan-Mei Liao ,  Kuei-Lun Lin ,  Jian-Hao Chen ,  Kuo-Feng Yu

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

公开(公告)号：US20190006483A1

公开(公告)日：2019-01-03

申请号：US16051002

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/2254 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US09577070B2

公开(公告)日：2017-02-21

申请号：US14555311

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/165

CPC classification number: H01L29/4983 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28247 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

Abstract translation: 讨论了用于形成诸如晶体管的器件的方法和结构。 方法实施例包括沿着衬底上的栅极堆叠的侧壁形成栅极间隔物; 钝化栅极隔离物的外表面的至少一部分; 并且在栅极间隔物附近外延生长衬底中的材料，同时栅极间隔物的外表面的至少部分保持钝化。 钝化可以包括使用热处理，等离子体处理或热处理中的至少一种。