公开(公告)号：US12230713B2

公开(公告)日：2025-02-18

申请号：US17410048

申请日：2021-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Wei Chen ,  Chi-Sheng Lai ,  Shih-Hao Lin ,  Jian-Hao Chen ,  Kuo-Feng Yu

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

公开(公告)号：US20240413221A1

公开(公告)日：2024-12-12

申请号：US18770408

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Chih-Yu Hsu ,  Hui-Chi Chen ,  Shan-Mei Liao ,  Jian-Hao Chen ,  Cheng-Hao Hou ,  Huang-Chin Chen ,  Cheng Hong Yang ,  Shih-Hao Lin ,  Tsung-Da Lin ,  Da-Yuan Lee ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Chi On Chui ,  Yen-Ming Chen

IPC: H01L29/423 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/417 ,  H01L29/51 ,  H01L29/786

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

公开(公告)号：US20240332382A1

公开(公告)日：2024-10-03

申请号：US18738303

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsiang Chan ,  Shan-Mei Liao ,  Wen-Hung Huang ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

公开(公告)号：US11777004B2

公开(公告)日：2023-10-03

申请号：US17313368

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  I-Wen Wu ,  Chen-Ming Lee ,  Jian-Hao Chen ,  Fu-Kai Yang ,  Feng-Cheng Yang ,  Mei-Yun Wang ,  Yen-Ming Chen

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/41791 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66795 ,  H01L29/7851

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

公开(公告)号：US20230063857A1

公开(公告)日：2023-03-02

申请号：US17461499

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Chih-Yu Hsu ,  Hui-Chi Chen ,  Shan-Mei Liao ,  Jian-Hao Chen ,  Cheng-Hao Hou ,  Huang-Chin Chen ,  Cheng Hong Yang ,  Shih-Hao Lin ,  Tsung-Da Lin ,  Da-Yuan Lee ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Chi On Chui ,  Yen-Ming Chen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/51 ,  H01L29/417 ,  H01L21/3105 ,  H01L29/40

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

公开(公告)号：US20230011783A1

公开(公告)日：2023-01-12

申请号：US17738378

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hang Chiu ,  Kuan-Ting Liu ,  Chi On Chui ,  Chia-Wei Chen ,  Jian-Hao Chen ,  Cheng-Lung Hung

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.

公开(公告)号：US20230010952A1

公开(公告)日：2023-01-12

申请号：US17737851

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Yen-Ju Chen ,  Chun-Chih Cheng

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

公开(公告)号：US20220336609A1

公开(公告)日：2022-10-20

申请号：US17233098

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsiang Chan ,  Wen-Hung Huang ,  Shan-Mei Liao ,  Kuei-Lun Lin ,  Jian-Hao Chen ,  Kuo-Feng Yu

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

公开(公告)号：US12218213B2

公开(公告)日：2025-02-04

申请号：US17677390

申请日：2022-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： An-Hung Tai ,  Jian-Hao Chen ,  Hui-Chi Chen ,  Kuo-Feng Yu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

公开(公告)号：US20240387682A1

公开(公告)日：2024-11-21

申请号：US18784523

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： An-Hung Tai ,  Yung-Hsiang Chan ,  Shan-Mei Liao ,  Hsin-Han Tsai ,  Jian-Hao Chen ,  Kuo-Feng Yu

IPC: H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes removing a dummy gate structure to expose a channel region, depositing an interface layer on the channel region, depositing a gate dielectric layer on the interface layer, and forming a doping layer on the gate dielectric layer. The doping layer includes a dipole-inducing element. The method also includes annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer, removing the doping layer, forming a work function metal layer on the gate dielectric layer, depositing an oxygen blocking layer on the work function metal layer, and forming a gate metal fill layer on the oxygen blocking layer.