公开(公告)号：US20230387198A1

公开(公告)日：2023-11-30

申请号：US18366210

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

公开(公告)号：US20220123126A1

公开(公告)日：2022-04-21

申请号：US17567492

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Lin ,  Yen-Ting Chen ,  Wen-Kai Lin ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

公开(公告)号：US11217679B2

公开(公告)日：2022-01-04

申请号：US16837554

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Lin ,  Yen-Ting Chen ,  Wen-Kai Lin ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

公开(公告)号：US20210313441A1

公开(公告)日：2021-10-07

申请号：US16837554

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Lin ,  Yen-Ting Chen ,  Wen-Kai Lin ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

公开(公告)号：US20150340293A1

公开(公告)日：2015-11-26

申请号：US14815375

申请日：2015-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Lung Cheng ,  Da-Wen Lin ,  Yen-Chun Lin

IPC: H01L21/8238 ,  H01L21/324 ,  H01L29/51 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

Abstract translation: 各种方法包括提供基板，形成从基板向上延伸的突起，突起在其中具有通道区域，以及形成接合邻近通道区域的突起的栅极结构，栅极结构具有间隔开的第一和第二导电层以及 应变诱发导电层设置在第一和第二导电层之间。 所述方法还包括在所述栅极结构的每一侧的所述突起的部分上形成外延生长，所述外延生长对所述沟道区赋予第一应变，并且向所述沟道区赋予第二应变，包括执行至少一个应力记忆技术 在栅极结构上使得应变诱导导电层将第二应变施加到沟道区，并且去除覆盖层，其中赋予第二应变以赋予沟道区的拉伸应变的方式进行。

公开(公告)号：US12191370B2

公开(公告)日：2025-01-07

申请号：US17714528

申请日：2022-04-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Yu Lai ,  Wei-Yang Lee ,  Ming-Lung Cheng ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.

公开(公告)号：US20230352530A1

公开(公告)日：2023-11-02

申请号：US18341334

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775 ,  H01L29/08

CPC classification number: H01L29/0673 ,  H01L29/66636 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/0847 ,  H01L29/42392

Abstract: The method includes receiving a semiconductor workpiece having active regions extending above a top surface of a semiconductor substrate, forming first dielectric features on first opposing sidewalls of the active regions across a first direction, forming second dielectric features extending between opposing sidewalls of the first dielectric features, and etching portions of the active region to form source/drain trenches. The source/drain trenches expose second opposing sidewalls of the active region. The method further includes recessing the first dielectric features and forming source/drain features in the source/drain trenches and on the exposed second opposing sidewalls of the active region. The source/drain features are partially formed on top surfaces of the first dielectric features.

公开(公告)号：US20220328623A1

公开(公告)日：2022-10-13

申请号：US17226896

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

公开(公告)号：US09768277B2

公开(公告)日：2017-09-19

申请号：US14815375

申请日：2015-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Lung Cheng ,  Da-Wen Lin ,  Yen-Chun Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

公开(公告)号：US12154946B2

公开(公告)日：2024-11-26

申请号：US18315578

申请日：2023-05-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Shuan Li ,  Ming-Lung Cheng

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The semiconductor device structure also includes a first gate structure wrapping around the first nanostructures. The semiconductor device structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The semiconductor device structure further includes a first inner spacer extending from the first gate structure to the first source/drain epitaxial structure by a first distance. The semiconductor device structure also includes second nanostructures formed over the first nanostructures. The semiconductor device structure further includes a second gate structure wrapping around the second nanostructures. The semiconductor device structure also includes a second source/drain epitaxial structure formed beside the second nanostructures. The semiconductor device structure further includes a second inner spacer extending from the second gate structure to the second source/drain epitaxial structure by a second distance, wherein the second distance is different from the first distance.