公开(公告)号：US20180350689A1

公开(公告)日：2018-12-06

申请号：US16101478

申请日：2018-08-12

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L21/8221 ,  G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  G11C29/82 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796

摘要： A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors and forming a plurality of logic gates; a first intermediate metal layer overlaying the at least one metal layer; a second intermediate metal layer overlaying the first intermediate metal layer; where the first intermediate metal layer has a first current carrying capacity, where the second intermediate metal layer has a second current carrying capacity, and where the first current carrying capacity is significantly greater than the second current carrying capacity; a plurality of second transistors overlaying the second intermediate metal layer; and a top metal layer overlaying the second transistors; and a memory cell, where at least one of the second transistors includes a polysilicon transistor channel, where the second transistors are precisely aligned to the first transistors.

公开(公告)号：US20180343735A1

公开(公告)日：2018-11-29

申请号：US15987950

申请日：2018-05-24

申请人： Osram GmbH

发明人： Philipp Helbig ,  Sebastian Jooss

IPC分类号： H05K1/02 ,  H01L23/367 ,  H01L23/498 ,  F21V29/70 ,  H05K3/34 ,  H05K1/14

CPC分类号： H05K1/0201 ,  F21V29/70 ,  F21Y2115/10 ,  H01L23/3677 ,  H01L23/49838 ,  H01L25/0753 ,  H01L33/62 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2924/19107 ,  H01L2933/0075 ,  H05K1/0204 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/145 ,  H05K1/183 ,  H05K3/0061 ,  H05K3/341 ,  H01L2924/00014

摘要： An electronic assembly for lighting applications. The assembly includes a printed circuit board (PCB) having a first PCB surface, which is designed for populating with electronic components, and a second PCB surface opposite the first PCB surface. The PCB has a continuous cutout from the first PCB surface to the second PCB surface. The electronic assembly further includes a heat distributor having at least one first contact surface and at least one second contact surface opposite the first contact surface. The first contact surface is connected in a material-bonded manner to the PCB arranged in parallel therewith at the second printed circuit board surface. The electronic assembly further includes at least one first light emitting diode element, which is arranged on a section of the first contact surface, which section is exposed within the cutout, and is connected in a material-bonded manner to the first contact surface.

公开(公告)号：US20180269158A1

公开(公告)日：2018-09-20

申请号：US15985640

申请日：2018-05-21

申请人： NXP USA, Inc.

发明人： Shun Meen Kuo ,  Paul R. Hart ,  Margaret A. Szymanowski

IPC分类号： H01L23/552 ,  H01L23/00 ,  H03F1/02 ,  H03F3/195 ,  H03F3/21 ,  H01L23/66

CPC分类号： H01L23/552 ,  H01L23/66 ,  H01L24/04 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6661 ,  H01L2224/04042 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/19107 ,  H01L2924/30111 ,  H03F1/0288 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/222 ,  H03F2200/387 ,  H01L2924/00014 ,  H01L2924/00

摘要： A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

公开(公告)号：US10074621B2

公开(公告)日：2018-09-11

申请号：US15181489

申请日：2016-06-14

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Chih-Hsien Chiu ,  Chi-Pin Tsai ,  Chi-Liang Shih ,  Ming-Fan Tsai ,  Chia-Yang Chen

IPC分类号： H01L23/48 ,  H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/66 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.

公开(公告)号：US20180255643A1

公开(公告)日：2018-09-06

申请号：US15889491

申请日：2018-02-06

申请人： Skyworks Solutions, Inc.

发明人： Darren Roger Frenette ,  George Khoury ,  Leslie Paul Wallis ,  Lori Ann DeOrio

IPC分类号： H05K1/18 ,  H03F3/195 ,  H03H7/06 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/66 ,  H04B1/40 ,  H03F3/213

CPC分类号： H05K1/181 ,  H01L23/3107 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L25/18 ,  H01L41/0475 ,  H01L41/113 ,  H01L2223/6644 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48225 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/146 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03B5/32 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451 ,  H03H7/06 ,  H03H9/0547 ,  H03H2001/0021 ,  H04B1/40 ,  H05K2201/1006 ,  H05K2201/10098 ,  H05K2201/10674 ,  H01L2224/45099

摘要： A packaged module for use in a wireless communication device has a substrate supporting an integrated circuit die that includes at least a microprocessor and radio frequency receiver circuitry and a stacked filter assembly configured as a filter circuit that is in communication with the radio frequency receiver circuitry. The stacked filter assembly includes a plurality of passive components, where each passive component is packaged as a surface mount device. At least one passive component is in direct communication with the substrate and at least another passive component is supported above the substrate by the at least one passive component that is in the direct communication with the substrate.

公开(公告)号：US20180247923A1

公开(公告)日：2018-08-30

申请号：US15967233

申请日：2018-04-30

申请人： ABB Schweiz AG

发明人： Samuel Hartmann ,  Ulrich Schlapbach

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC分类号： H01L25/18 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5381 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate, wherein the diode chip is electrically connected antiparallel to the semiconductor switch chip; wherein the semiconductor switch chip is electrically connected via bond wires to an emitter conductor on the substrate plate providing a first emitter current path, which emitter conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; wherein a gate electrode of the semiconductor switch chip is electrically connected via a bond wire to a gate conductor on the substrate plate providing a gate current path, which gate conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; and wherein a protruding area of the emitter conductor runs besides the diode chip towards the first semiconductor switch chip and the first semiconductor switch chip is directly connected via a bond wire with the protruding area providing an additional emitter current path running at least partially along the gate current path. The semiconductor switch chip is a first semiconductor switch chip and the diode chip is a first diode chip, which are arranged in a first row. The semiconductor module comprises further a second row of a second semiconductor switch chip and a second diode chip attached to the collector conductor, wherein the diode chip of each row is electrically connected antiparallel to the semiconductor switch chip of the same row and the first and second rows are electrically connected in parallel. The first semiconductor switch chip is arranged besides the second diode chip and the second semiconductor chip is arranged besides the first diode chip.

公开(公告)号：US10062661B2

公开(公告)日：2018-08-28

申请号：US15628851

申请日：2017-06-21

申请人： Tessera, Inc.

发明人： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC分类号： H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L27/146 ,  H01L25/04 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L24/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00

摘要： Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

公开(公告)号：US20180211938A1

公开(公告)日：2018-07-26

申请号：US15500138

申请日：2015-06-08

申请人： Hitachi Automotive Systems, Ltd.

发明人： Nobutake TSUYUNO ,  Junpei KUSUKAWA ,  Takeshi TOKUYAMA ,  Tokihito SUWA

IPC分类号： H01L25/07 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H02M7/00 ,  H02M7/537

CPC分类号： H01L25/072 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/49575 ,  H01L23/5385 ,  H01L24/37 ,  H01L24/40 ,  H01L25/18 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/33 ,  H01L2224/37599 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M7/003 ,  H02M7/537 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/37099 ,  H01L2224/45099

摘要： It is an object of the present invention to provide a power module which can withstand a high voltage with a thin insulating layer. A power module of the present invention is provided with a first power semiconductor element 328 of an upper arm side constituting an inverter circuit, a second power semiconductor element 330 of a lower arm side, a first conductor part 320 which transmits an alternating current, a second conductor part 315 which transmits a direct current, an electrically-conductive heat dissipating part 307, a first intermediate conductor layer 910 disposed between the first conductor part 320 and the heat dissipating part 307 via an insulating layer 900, and a second intermediate conductor layer 911 disposed between the second conductor part 315 and the heat dissipating part 307 via the insulating layer 900, wherein, the second intermediate conductor layer 911 is formed to be separated from the first intermediate conductor layer 910, and the first intermediate conductor layer 910 forms a capacity circuit which shares the voltage between the first conductor part 320 and the heat dissipating part 307.

公开(公告)号：US20180197834A1

公开(公告)日：2018-07-12

申请号：US15914617

申请日：2018-03-07

申请人： Invensas Corporation

发明人： Shaowu Huang ,  Javier A. Delacruz

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/566 ,  H01L23/3121 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014

摘要： Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

公开(公告)号：US10020284B2

公开(公告)日：2018-07-10

申请号：US14867893

申请日：2015-09-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd. ,  Global Unichip Corp.

发明人： Yu-Ru Chang ,  Chung-Kai Wang ,  Ming-Che Wu

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/065 ,  H01L21/308 ,  H01L21/78 ,  H01L23/498 ,  H01L23/552

CPC分类号： H01L24/97 ,  H01L21/308 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15156 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.