公开(公告)号：US12051730B2

公开(公告)日：2024-07-30

申请号：US17189093

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang Shih ,  Sung-Li Wang ,  Pang-Yen Tsai

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76202 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/66545

Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

公开(公告)号：US12046662B2

公开(公告)日：2024-07-23

申请号：US18307187

申请日：2023-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko Jangjian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/762 ,  H01L21/768 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/28556 ,  H01L21/762 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76843 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/76224 ,  H01L29/165

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the contact layer passes through the first barrier layer, the first barrier layer passes through the second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of a sidewall of the first barrier layer and exposes a first lower portion of the sidewall of the first barrier layer, and the sidewall faces away from the contact layer.

公开(公告)号：US12046518B2

公开(公告)日：2024-07-23

申请号：US17693183

申请日：2022-03-11

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Yong Li

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66795 ,  H01L21/0228 ,  H01L29/7848

Abstract: The present application discloses a method for manufacturing a fin field effect transistor, comprising: step 1: forming fins; step 2, forming first gate structures; and step 3, forming source and drain areas, comprising: step 31: forming a second hard mask layer; step 32: opening a formation area of FinFET, and performing the first time etching on the second hard mask layer; step 33: performing the second time etching to form first grooves in the fins, wherein the second time etching vertically and horizontally etches the isolation dielectric layer, when the second groove is formed next to the exposed surfaces of the isolation dielectric layer, the exposed surfaces of the fins and the first polysilicon gate, as the result, the second groove forms a bridge path; step 34: forming a sacrificial sidewall to fully fill the bridge path; and step 35: filling the first groove with an epitaxial layer.

公开(公告)号：US12040237B2

公开(公告)日：2024-07-16

申请号：US17752080

申请日：2022-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Heng Tsai ,  Chun-Sheng Liang ,  Pei-Lin Wu ,  Yi-Ren Chen ,  Shih-Hsun Chang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/7848 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823481

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.

公开(公告)号：US12035532B2

公开(公告)日：2024-07-09

申请号：US17149727

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chih-Chieh Yeh

IPC: H01L27/1157 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H10B43/35

CPC classification number: H10B43/35 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/792

Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

公开(公告)号：US20240204050A1

公开(公告)日：2024-06-20

申请号：US18588586

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongki JUNG ,  Myungil KANG ,  Yoonhae KIM ,  Kwanheum LEE

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.

公开(公告)号：US20240203987A1

公开(公告)日：2024-06-20

申请号：US18415143

申请日：2024-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing LEE ,  Kun-Mu LI ,  Ming-Hua YU ,  Tsz-Mei KWOK

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/7848

Abstract: An IC structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. The first epitaxial structure is on the first structure. The first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. The second epitaxial structure is on the second fin structure. The second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

公开(公告)号：US20240203734A1

公开(公告)日：2024-06-20

申请号：US18540329

申请日：2023-12-14

Applicant: ASM IP Holding B.V.

Inventor： Maritza Mujica ,  Ernesto Suarez ,  Amir Kajbafvala ,  Rami Khazaka ,  Arum Murali ,  Frederick Aryeetey ,  Yanfu Lu ,  Caleb Miskin ,  Alexandros Demos ,  Bibek Karki

IPC: H01L21/02 ,  C30B25/10 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L29/78

CPC classification number: H01L21/0262 ,  C30B25/10 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/7848 ,  H01L29/167

Abstract: Methods for forming multilayer structures are disclosed. The methods may include, seating a substrate within a chamber body, and regulating a temperature profile across an upper surface of the substrate during each individual deposition phase of multiphase deposition process. Semiconductor device structures including multilayer structures are also disclosed.

公开(公告)号：US12009427B2

公开(公告)日：2024-06-11

申请号：US17978027

申请日：2022-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/3115 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02255

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

公开(公告)号：US12009394B2

公开(公告)日：2024-06-11

申请号：US18083792

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02236 ,  H01L21/02603 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.