公开(公告)号：US20150156881A1

公开(公告)日：2015-06-04

申请号：US14555856

申请日：2014-11-28

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Yuichi NAKAMURA ,  Tsuyoshi YAMAGUCHI

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/06152 ,  H01L2224/06153 ,  H01L2224/12105 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/181 ,  H05K1/185 ,  H05K3/30 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/4913

Abstract: A substrate with a built-in electronic component includes multiple resin insulating layers including first, second, third and fourth insulating layers, multiple conductor layers including a first wiring layer including a first pad, a second wiring layer including a second pad, and a third wiring layer including third and fourth pads, multiple via conductors including a first via connecting the first and second pads through the second insulating layer, a second via connecting the second and third pads through the third and fourth insulating layers, and a third via connected to the fourth pad through the fourth insulating layer, and an electronic component positioned a cavity through the second and third insulating layers such that the third via is connecting terminal of the component and fourth pad. The second and third vias have filled plating filling opening portions through the third and fourth insulating layers and through the fourth insulating layer.

Abstract translation: 具有内置电子部件的基板包括包括第一，第二，第三和第四绝缘层的多个树脂绝缘层，多个导体层，包括包括第一焊盘的第一布线层，包括第二焊盘的第二布线层和第三焊盘的第三布线层 包括第三和第四焊盘的布线层，多个通孔导体，包括通过第二绝缘层连接第一和第二焊盘的第一通孔，通过第三和第四绝缘层连接第二和第三焊盘的第二通孔，以及连接到 通过第四绝缘层的第四焊盘和通过第二和第三绝缘层定位空腔的电子部件，使得第三通孔是部件和第四焊盘的连接端子。 第二和第三通孔已经通过第三绝缘层和第四绝缘层填充电镀填充开口部分并穿过第四绝缘层。

公开(公告)号：US20150084186A1

公开(公告)日：2015-03-26

申请号：US14507189

申请日：2014-10-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Horng CHANG ,  Tin-Hao KUO ,  Chen-Shien CHEN ,  Yen-Liang LIN

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill.

Abstract translation: 凸块结构包括第一端和与第一端相对的第二端。 凸起结构还包括连接在第一端和第二端之间的第一侧。 凸起结构还包括与第一侧相对的第二侧。 第二侧连接在第一端和第二端之间，第二侧包括用于填充回流焊料的凹部。

公开(公告)号：US20150069602A1

公开(公告)日：2015-03-12

申请号：US14549551

申请日：2014-11-21

Applicant: Novatek Microelectronics Corp.

Inventor： Chiao-Ling Huang ,  Tai-Hung Lin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/061 ,  H01L2224/06153 ,  H01L2224/13008 ,  H01L2224/13016 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/13144 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29082 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A chip-on-film device including a flexible circuit film having a wire, a passivation layer having a hole, an adhesive layer, a first pad, a second pad, an interconnection, and a bump is provided. A part of the adhesive layer is disposed in the hole. The first pad and the second pad are disposed under the passivation layer.A part of the interconnection is disposed under the passivation layer, and disposed between the first pad and the second pad. The bump is electrically connected to the first pad via the adhesive layer. The bump is welded on the wire. A part of a first part of the bump overlaps the first pad, a second part of the bump extends to an outside of the pad and at least partially overlaps the interconnection, and the third part of the bump overlaps the second pad.

Abstract translation: 提供了一种片上电影装置，其包括具有导线的柔性电路膜，具有孔的钝化层，粘合剂层，第一焊盘，第二焊盘，互连和凸块。 粘合剂层的一部分设置在孔中。 第一焊盘和第二焊盘设置在钝化层的下方。 互连的一部分设置在钝化层下方，并且设置在第一焊盘和第二焊盘之间。 凸块通过粘合剂层电连接到第一焊盘。 凸块焊接在电线上。 凸块的第一部分的一部分与第一焊盘重叠，凸块的第二部分延伸到焊盘的外部并且至少部分地与互连重叠，并且凸块的第三部分与第二焊盘重叠。

公开(公告)号：US20140312493A1

公开(公告)日：2014-10-23

申请号：US14320686

申请日：2014-07-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  H01L23/485

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.

Abstract translation: 一种提高半导体芯片的凸块电极与安装基板的配线之间的耦合可靠性的技术，更具体地说，即使在布线位于突起电极下方的顶部布线层中时也能保证凸块电极的平坦度的技术，由此 提高凸起电极和形成在玻璃基板上的布线之间的耦合的可靠性。 在突起电极的非重叠区域下方的顶部布线层中形成由电力线或信号线构成的布线和虚设图案。 虚拟图案位于填充布线之间的空间以减少由布线引起的不规则和顶部布线层中的空间。 形成为覆盖顶部布线层的冲浪保护膜被CMP平坦化。

公开(公告)号：US08829688B2

公开(公告)日：2014-09-09

申请号：US13680931

申请日：2012-11-19

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Yoshihiro Machida

IPC: H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/488 ,  H01L21/768 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11831 ,  H01L2224/11906 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2224/11

Abstract: A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide.

Abstract translation: 半导体器件包括布置有电极焊盘的半导体元件。 布线基板包括分别布置成与电极焊盘相对应的连接焊盘。 柱状电极端子分别形成在半导体元件的电极焊盘上。 焊接点电连接每个电极端子的远端部分和布线基板上的对应的连接焊盘。 每个电极端子包括连接到相应的电极焊盘的基部和形成在远端部分中的引导件。 如上所述，导向件具有比基部更小的横截面面积。 引导件具有圆周，并且基部具有与引导件的圆周部分齐平的圆周。 引导件被形成以引导焊料朝向引导件的圆周。

公开(公告)号：US08701972B2

公开(公告)日：2014-04-22

申请号：US14013304

申请日：2013-08-29

Applicant: Reneasas Electronics Corporation

Inventor： Takafumi Nishita ,  Nobuhiro Kinoshita ,  Jumpei Konno ,  Michiaki Sugiyama ,  Kazunori Hasegawa

IPC: H01L21/60 ,  B23K31/02

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract translation: 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。

公开(公告)号：US20130292821A1

公开(公告)日：2013-11-07

申请号：US13793241

申请日：2013-03-11

Applicant: CHIPMOS TECHNOLOGIES INC.

Inventor： Chung-Pang CHI

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/768 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/061 ,  H01L2224/06163 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2924/381 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.

Abstract translation: 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括多个第一焊盘和第二焊盘。 焊盘区域被限定有第一区域，第二区域和第三区域，其中第一区域位于第二区域和第三区域之间。 第一焊盘和第二焊盘中的每一个在第一区域上彼此交错。 导电结构包括分别形成在每个第一焊盘和第二焊盘上的多个导电凸块，以与第一焊盘和第二焊盘中的每一个电连接。 每个导电凸块具有设置在第一区域上的第一凸起宽度和设置在第一凸起宽度比第二凸起宽度短的第二和第三区域中的一个上的第二凸起宽度。

公开(公告)号：US20130292819A1

公开(公告)日：2013-11-07

申请号：US13659932

申请日：2012-10-25

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chiao-Ling Huang ,  Tai-Hung Lin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/061 ,  H01L2224/06153 ,  H01L2224/13008 ,  H01L2224/13016 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/13144 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29082 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A chip-on-film device including a flexible circuit film having a wire, a passivation layer having a hole, an adhesive layer, a pad, an interconnection, and a bump is provided. A part of the adhesive layer is disposed in the hole. The pad is disposed under the passivation layer, and a part of the pad is disposed under the hole. A part of the interconnection is disposed under the passivation layer, and disposed at a side of the pad, wherein the interconnection does not touch the pad. A part of the bump is disposed on the adhesive layer. The bump is electrically connected to the pad via the adhesive layer. The bump is welded on the wire. A part of a first part of the bump overlaps the pad, and a second part of the bump extends to an outside of the pad and at least partially overlaps the interconnection.

Abstract translation: 提供了一种包括具有线的柔性电路膜，具有孔的钝化层，粘合剂层，衬垫，互连和凸块的片上电影设备。 粘合剂层的一部分设置在孔中。 焊盘设置在钝化层下方，并且焊盘的一部分设置在孔的下方。 互连的一部分设置在钝化层下方，并且设置在焊盘的一侧，其中互连不接触焊盘。 凸块的一部分设置在粘合剂层上。 凸块通过粘合剂层电连接到焊盘。 凸块焊接在电线上。 凸块的第一部分的一部分与焊盘重叠，并且凸块的第二部分延伸到焊盘的外部并且至少部分地重叠互连。

公开(公告)号：US20120007235A1

公开(公告)日：2012-01-12

申请号：US13106879

申请日：2011-05-13

Applicant: Chao-Chih Hsiao ,  Po-Ching Li

Inventor： Chao-Chih Hsiao ,  Po-Ching Li

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/4985 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00

Abstract: A chip fanning out method is disclosed. The chip fanning out method includes mounting a chip on a film, forming a plurality of outer lead bonds spatially arranged in a bump correspondence order on the film, forming a plurality of bumps spatially arranged in a bump arrangement order on the chip, and forming a plurality of wires to connect the plurality of outer lead bonds to the plurality of bumps according to the bump correspondence order, wherein the bump correspondence order is different from the bump arrangement order.

Abstract translation: 公开了一种芯片扇出方法。 芯片扇出方法包括将芯片安装在薄膜上，在薄膜上形成以凸起对应的顺序空间上排列的多个外部引线键，形成以芯片上的凸块布置顺序空间排列的多个凸起，并形成 多个导线，根据凸点对应次序将多个外部引线接合部连接到多个凸起部，其中凸起对应次序不同于凸块布置次序。

公开(公告)号：US12087718B2

公开(公告)日：2024-09-10

申请号：US18300493

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16056 ,  H01L2224/16059 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/384 ,  Y10T428/12493 ,  Y10T428/24479

Abstract: The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.