公开(公告)号：US12068191B2

公开(公告)日：2024-08-20

申请号：US18068041

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/285 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/76805 ,  H01L21/0332 ,  H01L21/283 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/66545 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/823425 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

公开(公告)号：US20240274687A1

公开(公告)日：2024-08-15

申请号：US18647521

申请日：2024-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hung CHU ,  Kan-Ju Lin ,  Hsu-Kai Chang ,  Chien Chang ,  Tzu-Pei Chen ,  Hung-Yi Huang ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/45 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/31116 ,  H01L21/823475 ,  H01L23/53242 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US12062724B2

公开(公告)日：2024-08-13

申请号：US18243691

申请日：2023-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masahiro Watanabe ,  Mitsuo Mashiyama ,  Kenichi Okazaki ,  Motoki Nakashima ,  Hideyuki Kishida

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823475 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/1233 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78672

Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

公开(公告)号：US12062611B2

公开(公告)日：2024-08-13

申请号：US17665703

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US12062574B2

公开(公告)日：2024-08-13

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US20240266394A1

公开(公告)日：2024-08-08

申请号：US18639948

申请日：2024-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Young LEE ,  Jin Wook LEE

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0669 ,  H01L21/76895 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a source/drain pattern disposed on a substrate and a source/drain contact connected to the source/drain pattern. The source/drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, and each of the first sub-sidewalls includes a concave surface.

公开(公告)号：US20240251537A1

公开(公告)日：2024-07-25

申请号：US18428994

申请日：2024-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Dian-Sheg Yu ,  Ren-Fen Tsui ,  Jhon Jhy Liaw

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76802 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0203 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L21/76814 ,  H01L21/76897 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H10B10/18

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

公开(公告)号：US20240243188A1

公开(公告)日：2024-07-18

申请号：US18513759

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon KIM ,  Unki KIM ,  Pankwi PARK ,  Sungkeun LIM ,  Yuyeong JO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.

公开(公告)号：US20240243065A1

公开(公告)日：2024-07-18

申请号：US18623806

申请日：2024-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei WU ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L23/528 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L29/0696

Abstract: A device includes: at a front side of a substrate, a first conductive line; and at a back side of the substrate, first to fifth power rails in a same back side metal layer; and wherein, within a span of a first cell, the second power rail is between the third and fourth power rails; each of the first to fifth power rails is configured different reference voltages first to third reference voltages, the first conductive line is configured to receive a control signal, an input signal, an output signal or one of the reference voltages; and relative to a center of the second power rail, a distribution of the first, second and third reference voltages amongst the first to fifth power rails is (A) symmetric with respect to a first direction and (B) symmetric with respect to perpendicular second direction.

公开(公告)号：US20240243009A1

公开(公告)日：2024-07-18

申请号：US18618815

申请日：2024-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: A device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. The source/drain regions are over a substrate. The gate structure is between the source/drain regions. The source/drain contact is over one of the source/drain regions. The tungsten structure is over the source/drain contact. The tungsten structure includes a lower portion and an upper portion above the lower portion. The upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.