公开(公告)号：US20130241030A1

公开(公告)日：2013-09-19

申请号：US13886556

申请日：2013-05-03

Applicant: STATS CHIPPAC, LTD.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

Abstract translation: 半导体器件具有形成在基底基板的第一表面中的凹部的基底基板。 第一导电层形成在第一表面上并进入凹槽中。 在基底基板的第二表面上形成第二导电层。 第一半导体管芯安装到基底基板上，凸起部分设置在第一导电层的凹槽内。 第二半导体管芯安装到第一半导体管芯。 在第二半导体管芯和第一导电层之间的基底衬底的第一表面上形成接合线。 密封剂沉积在第一和第二半导体管芯和基底衬底上。 基底基板的一部分从第二导电层之间的第二表面移除到凹部，以形成用于凸块和接合线的电隔离的基底引线。

公开(公告)号：US09824975B2

公开(公告)日：2017-11-21

申请号：US14612075

申请日：2015-02-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/538 ,  H01L25/07 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant.

公开(公告)号：US09640504B2

公开(公告)日：2017-05-02

申请号：US14224931

申请日：2014-03-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L24/18 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1902 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

公开(公告)号：US09601369B2

公开(公告)日：2017-03-21

申请号：US14249307

申请日：2014-04-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Reza A. Pagaila

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be electrically interconnected through the TSVs.

公开(公告)号：US09431331B2

公开(公告)日：2016-08-30

申请号：US13937849

申请日：2013-07-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Reza A. Pagaila ,  Linda Pei Ee Chua

IPC: H01L23/50 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3011 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps.

公开(公告)号：US20160111410A1

公开(公告)日：2016-04-21

申请号：US14971291

申请日：2015-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

公开(公告)号：US20150279815A1

公开(公告)日：2015-10-01

申请号：US14228769

申请日：2014-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Sung Soo Kim

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01082 ,  H01L2224/81805 ,  H01L2224/45099

Abstract: A semiconductor device has a first conductive layer disposed over a carrier. A second conductive layer is formed over a first surface of the first conductive layer. A first insulating layer is formed over the first and second conductive layers. A third conductive layer is formed over the first insulating layer. A second insulating layer is formed over the third conductive layer. The carrier is removed to expose the first conductive layer. A portion of the first conductive layer is removed from a second surface of the first conductive layer opposite the first surface to form a plurality of conductive pillars. The conductive pillars include a height of 100 micrometers or greater. The portion of the first conductive layer is removed using an etching process. The conductive pillars are disposed over a first semiconductor package. A semiconductor die or second semiconductor package is disposed over the second conductive layer.

Abstract translation: 半导体器件具有设置在载体上的第一导电层。 在第一导电层的第一表面上形成第二导电层。 在第一和第二导电层上形成第一绝缘层。 在第一绝缘层上形成第三导电层。 在第三导电层上形成第二绝缘层。 移除载体以露出第一导电层。 第一导电层的一部分从与第一表面相对的第一导电层的第二表面去除以形成多个导电柱。 导电柱包括100微米或更大的高度。 使用蚀刻工艺去除第一导电层的部分。 导电柱设置在第一半导体封装之上。 半导体管芯或第二半导体封装设置在第二导电层上。

公开(公告)号：US20150228628A1

公开(公告)日：2015-08-13

申请号：US14694811

申请日：2015-04-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Abstract translation: 半导体器件具有形成在半导体管芯的第一表面上的第一导热层。 半导体管芯的第二表面安装到牺牲载体上。 密封剂沉积在第一导热层和牺牲载体上。 将密封剂平坦化以暴露第一导热层。 第一绝缘层形成在半导体管芯的第二表面和密封剂的第一表面上。 半导体管芯的第二表面上的第一绝缘层的一部分被去除。 在第一绝缘层的去除部分内的半导体管芯的第二表面上形成第二导热层。 在第二导热层周围的绝缘层内形成导电层。 散热器可以安装在第一导热层上。

公开(公告)号：US20140008769A1

公开(公告)日：2014-01-09

申请号：US14021206

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/315 ,  H01L23/66 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract translation: 半导体晶片具有多个具有应力敏感区域的第一半导体管芯。 掩模层或屏幕设置在应力敏感区域上方。 底部填充材料沉积在晶片上。 掩蔽层或屏幕防止邻近敏感区域形成底部填充材料。 去除掩模层或屏幕，留下邻近敏感区域的底部填充材料中的空腔。 将半导体晶片分割成第一模具。 第一管芯可以安装到堆积互连结构或第二半导体管芯，其中空腔分离敏感区域并建立互连结构或第二管芯。 在第一和第二管芯之间形成接合线，并且密封剂沉积在第一和第二管芯和接合线上。 可以通过第一或第二管芯形成导电通孔。

公开(公告)号：US20130214385A1

公开(公告)日：2013-08-22

申请号：US13845409

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan ,  Seng Guan Chow

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Abstract translation: 半导体器件包括具有顶部，底部和外围表面的第一裸片。 在顶表面上形成接合垫。 有机材料连接到第一模具并围绕周边表面设置。 在有机材料中形成通孔。 金属迹线将通孔连接到接合垫。 导电材料沉积在通孔中。 再分布层（RDL）具有设置在第一管芯的顶表面上的互连焊盘。