公开(公告)号：US20240006236A1

公开(公告)日：2024-01-04

申请号：US18133065

申请日：2023-04-11

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Junyeong YUN ,  Rongjun WANG ,  Yi XU ,  Yu LEI ,  Wenting HOU ,  Xianmin TANG

IPC: H01L21/768 ,  H01J37/32

CPC classification number: H01L21/76876 ,  H01J37/321 ,  H01L21/76843 ,  H01L21/76895 ,  H01J2237/338 ,  H01J37/32899

Abstract: A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one feature. The method includes forming the nucleation layer via a cyclic vapor deposition process. The cyclic vapor deposition process includes forming a portion of the nucleation layer and then exposing the exposing the nucleation layer a chemical vapor transport (CVT) process to remove impurities from the portion of the nucleation layer. The CVT process may be performed at a temperature of 400 degrees Celsius or less and comprises forming a plasma from a processing gas comprising greater than or equal to 90% of hydrogen gas of a total flow of hydrogen gas and oxygen.

公开(公告)号：US20230377892A1

公开(公告)日：2023-11-23

申请号：US17748329

申请日：2022-05-19

Applicant: Applied Materials, Inc.

Inventor： Yiyang WAN ,  Weifeng YE ,  Shumao ZHANG ,  Gary HOW ,  Jiang LU ,  Lei ZHOU ,  Dien-yeh WU ,  Douglas LONG ,  Avgerinos V. GELATOS ,  Ying-Bing JIANG ,  Rongjun WANG ,  Xianmin TANG ,  Halbert CHONG

IPC: H01L21/285 ,  H01J37/32 ,  C23C16/42 ,  C23C16/507

CPC classification number: H01L21/28518 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32357 ,  C23C16/42 ,  C23C16/507 ,  H01J37/32816 ,  H01J2237/332

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate comprises forming a plasma reaction between titanium tetrachloride (TlCl4), hydrogen (H2), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.

公开(公告)号：US20230122956A1

公开(公告)日：2023-04-20

申请号：US17506075

申请日：2021-10-20

Applicant: Applied Materials, Inc.

Inventor： Zhiyong WANG ,  Halbert CHONG ,  John C. FORSTER ,  Irena H. WYSOK ,  Tiefeng SHI ,  Gang FU ,  Renu WHIG ,  Keith A. MILLER ,  Sundarapandian Ramalinga Vijayalakshmi REDDY ,  Jianxin LEI ,  Rongjun WANG ,  Tza-Jing GUNG ,  Kirankumar Neelasandra SAVANDAIAH ,  Avinash NAYAK ,  Lei ZHOU

IPC: C23C14/34 ,  H01J37/32

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a processing chamber for processing a substrate comprises a sputtering target, a chamber wall at least partially defining an inner volume within the processing chamber and connected to ground, a power source comprising an RF power source, a process kit surrounding the sputtering target and a substrate support, an auto capacitor tuner (ACT) connected to ground and the sputtering target, and a controller configured to energize the cleaning gas disposed in the inner volume of the processing chamber to create the plasma and tune the sputtering target using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit during the etch process to remove sputtering material from the process kit, wherein the predetermined potential difference is based on a resonant point of the ACT.

公开(公告)号：US20210320246A1

公开(公告)日：2021-10-14

申请号：US16845600

申请日：2020-04-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Xiaodong WANG ,  Renu WHIG ,  Jianxin LEI ,  Rongjun WANG

IPC: H01L43/12 ,  H01L43/10

Abstract: A method of forming a tunnel layer of a magnetoresistive random-access memory (MRAM) structure includes forming a first magnesium oxide (MgO) layer by sputtering an MgO target using radio frequency (RF) power, exposing the first MgO layer to oxygen for approximately 5 seconds to approximately 20 seconds at a flow rate of approximately 10 sccm to approximately 15 sccm, and forming a second MgO layer on the first MgO layer by sputtering the MgO target using RF power. The method may be performed after periodic maintenance of a process chamber to increase the tunnel magnetoresistance (TMR) of the tunnel layer.

公开(公告)号：US20210193914A1

公开(公告)日：2021-06-24

申请号：US17193966

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Rongjun WANG ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L27/22

Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

公开(公告)号：US20170253959A1

公开(公告)日：2017-09-07

申请号：US15448996

申请日：2017-03-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Xiaodong WANG ,  Joung Joo LEE ,  Fuhong ZHANG ,  Martin Lee RIKER ,  Keith A. MILLER ,  William FRUCHTERMAN ,  Rongjun WANG ,  Adolph Miller ALLEN ,  Shouyin ZHANG ,  Xianmin TANG

IPC: C23C14/35 ,  H01J37/34 ,  C23C14/54

CPC classification number: C23C14/351 ,  C23C14/54 ,  H01J37/3405 ,  H01J37/3447 ,  H01J37/3455 ,  H01J37/3458 ,  H01L21/2855 ,  H01L21/76871 ,  H01L21/76879

Abstract: Methods and apparatus for controlling the ion fraction in physical vapor deposition processes are disclosed. In some embodiments, a process chamber for processing a substrate having a given diameter includes: an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a rotatable magnetron above the target to form an annular plasma in the peripheral portion; a substrate support disposed in the interior volume to support a substrate having the given diameter; a first set of magnets disposed about the body to form substantially vertical magnetic field lines in the peripheral portion; a second set of magnets disposed about the body and above the substrate support to form magnetic field lines directed toward a center of the support surface; a first power source to electrically bias the target; and a second power source to electrically bias the substrate support.

公开(公告)号：US20150348773A1

公开(公告)日：2015-12-03

申请号：US14410790

申请日：2013-07-01

Applicant: Applied Materials, Inc.

Inventor： Mingwei ZHU ,  Nag B. PATIBANDLA ,  Rongjun WANG ,  Vivek AGRAWAL ,  Anantha SUBRAMANI ,  Daniel Lee DIEHL ,  Xianmin TANG

IPC: H01L21/02 ,  H01L21/322 ,  H01J37/34 ,  H01L21/3065

CPC classification number: H01L21/0254 ,  C23C14/0036 ,  C23C14/0641 ,  H01J37/3426 ,  H01J37/3467 ,  H01L21/02458 ,  H01L21/02631 ,  H01L21/3065 ,  H01L21/3228

Abstract: Embodiments of the invention described herein generally relate to an apparatus and methods for forming high quality buffer layers and Group III-V layers that are used to form a useful semiconductor device, such as a power device, light emitting diode (LED), laser diode (LD) or other useful device. Embodiments of the invention may also include an apparatus and methods for forming high quality buffer layers, Group III-V layers and electrode layers that are used to form a useful semiconductor device. In some embodiments, an apparatus and method includes the use of one or more cluster tools having one or more physical vapor deposition (PVD) chambers that are adapted to deposit a high quality aluminum nitride (AlN) buffer layer that has a high crystalline orientation on a surface of a plurality of substrates at the same time.

Abstract translation: 本文描述的本发明的实施例一般涉及用于形成高质量缓冲层的装置和方法，以及用于形成有用的半导体器件的III-V层，例如功率器件，发光二极管（LED），激光二极管 （LD）或其他有用的装置。 本发明的实施例还可以包括用于形成用于形成有用的半导体器件的高质量缓冲层，III-V族层和电极层的装置和方法。 在一些实施例中，装置和方法包括使用具有一个或多个物理气相沉积（PVD）室的一个或多个簇工具，其适于将具有高结晶取向的高质量氮化铝（AlN）缓冲层沉积在 同时是多个基板的表面。

公开(公告)号：US20150132551A1

公开(公告)日：2015-05-14

申请号：US14531549

申请日：2014-11-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Yong CAO ,  Daniel Lee DIEHL ,  Rongjun WANG ,  Xianmin TANG ,  Tai-Chou Papo CHEN ,  Tingjun XU

IPC: H01L31/0216 ,  H01L31/18 ,  H01L31/032 ,  C23C14/35

CPC classification number: H01L31/02161 ,  C23C14/0042 ,  C23C14/0084 ,  C23C14/0652 ,  C23C14/0676 ,  C23C14/35 ,  G02B1/115 ,  H01L31/02168 ,  H01L31/18 ,  Y02E10/50 ,  Y10T428/24942

Abstract: A method for forming an anti-reflective coating (ARC) includes positioning a substrate below a target and flowing a first gas to deposit a first portion of the graded ARC onto the substrate. The method includes gradually flowing a second gas to deposit a second portion of the graded ARC, and gradually flowing a third gas while simultaneously gradually decreasing the flow of the second gas to deposit a third portion of the graded ARC. The method also includes flowing the third gas after stopping the flow of the second gas to form a fourth portion of the graded ARC. In another embodiment a film stack having a substrate having a graded ARC disposed thereon is provided. The graded ARC includes a first portion, a second portion disposed on the first portion, a third portion disposed on the second portion, and a fourth portion disposed on the third portion.

Abstract translation: 用于形成抗反射涂层（ARC）的方法包括将基底定位在靶材下方并流动第一气体以将渐变ARC的第一部分沉积到基底上。 该方法包括逐渐流动第二气体以沉积分级ARC的第二部分，并逐渐流动第三气体，同时逐渐减少第二气体的流动以沉积渐变ARC的第三部分。 该方法还包括在停止第二气体的流动之后流动第三气体以形成分级ARC的第四部分。 在另一个实施例中，提供了具有设置在其上的具有分级ARC的基板的薄膜叠层。 分级ARC包括第一部分，设置在第一部分上的第二部分，设置在第二部分上的第三部分和设置在第三部分上的第四部分。

公开(公告)号：US20250079199A1

公开(公告)日：2025-03-06

申请号：US18458146

申请日：2023-08-29

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Sahil Jaykumar PATEL ,  Yu LEI ,  Wei LEI ,  Chih-Hsun HSU ,  Yi XU ,  Abulaiti HAIRISHA ,  Cong TRINH ,  Yixiong YANG ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Rongjun WANG

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/3213

Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

公开(公告)号：US20240420947A1

公开(公告)日：2024-12-19

申请号：US18210651

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Jiajie CEN ,  Sahil Jaykumar PATEL ,  Zhimin QI ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Wei LEI ,  Yi XU ,  Yu LEI ,  Tsung-Han YANG ,  Xiaodong WANG ,  Xiangjin XIE ,  Yixiong YANG ,  Kevin KASHEFI ,  Rongjun WANG

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.