公开(公告)号：US08592904B2

公开(公告)日：2013-11-26

申请号：US13588538

申请日：2012-08-17

申请人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L29/66

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有电源MOS.FET高侧开关和功率MOS.FET低侧开关串联连接的电路的非绝缘DC-DC转换器中，功率MOS.FET低侧开关和肖特基 与功率MOS.FET低侧开关并联连接的阻挡二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中心，并且在其两侧设置功率MOS.FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US08575733B2

公开(公告)日：2013-11-05

申请号：US13717464

申请日：2012-12-17

申请人： Renesas Electronics Corporation

发明人： Yohihiro Satou ,  Tomoaki Uno ,  Nobuyoshi Matsuura ,  Masaki Shiraishi

IPC分类号： H01L23/495

CPC分类号： H01L23/5386 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L29/4175 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  H05K7/02 ,  Y02B70/1466 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075 ,  H01L2924/20754

摘要： The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

摘要翻译： 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS.FET和用于低侧开关的功率MOS.FET串联连接。 在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。 三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。

公开(公告)号：US08432015B2

公开(公告)日：2013-04-30

申请号：US12677123

申请日：2008-09-12

申请人： Hiroaki Tanaka

发明人： Hiroaki Tanaka

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/7397 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48458 ,  H01L2224/4846 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4911 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/85181 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device (2) includes: a FLR (65) that is disposed on a semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.

摘要翻译： 半导体器件（2）包括：FLR（65），其设置在半导体衬底上以将半导体衬底分成内部区域和外部区域; 第一焊盘（24a〜24d），其设置在所述内部区域中，并且通过一端连接到所述外部电路的导线（14a至14d）连接到外部电路; 以及设置在所述外部区域中并且所述电线的另一端接合在其上的第二接合焊盘（26a至26d）。

公开(公告)号：US08350372B2

公开(公告)日：2013-01-08

申请号：US13372227

申请日：2012-02-13

申请人： Yukihiro Satou ,  Tomoaki Uno ,  Nobuyoshi Matsuura ,  Masaki Shiraishi

发明人： Yukihiro Satou ,  Tomoaki Uno ,  Nobuyoshi Matsuura ,  Masaki Shiraishi

IPC分类号： H01L23/495

CPC分类号： H01L23/5386 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L29/4175 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  H05K7/02 ,  Y02B70/1466 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075 ,  H01L2924/20754

摘要： The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

摘要翻译： 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS•FET和低边开关的功率MOS•FET串联连接。 在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。 三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。

公开(公告)号：US20120319109A1

公开(公告)日：2012-12-20

申请号：US13594949

申请日：2012-08-27

申请人： Ralf Otremba ,  Marco Seibt ,  Uwe Kirchner ,  Wolfgang Peinhopf ,  Michael Treu ,  Andreas Schloegl ,  Mario Feldvoss

发明人： Ralf Otremba ,  Marco Seibt ,  Uwe Kirchner ,  Wolfgang Peinhopf ,  Michael Treu ,  Andreas Schloegl ,  Mario Feldvoss

IPC分类号： H01L23/544

CPC分类号： H01L23/4952 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85

摘要： An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

摘要翻译： 电子设备及其制造。 一个实施例提供了在第一表面上具有控制电极和第一负载电极的半导体芯片以及在第二表面上的第二负载电极。 第一引线电耦合到控制电极。 第二引线电耦合到第一负载电极。 第三引线电耦合到第一负载电极，第三引线与第二引线分离。 第四引线电耦合到第二负载电极，第二和第三引线布置在第一和第四引线之间。

公开(公告)号：US08314484B2

公开(公告)日：2012-11-20

申请号：US12691175

申请日：2010-01-21

申请人： Ryoichi Kajiwara ,  Shigehisa Motowaki ,  Kazutoshi Ito ,  Toshiaki Ishii ,  Katsuo Arai ,  Takuya Nakajo ,  Hidemasa Kagii

发明人： Ryoichi Kajiwara ,  Shigehisa Motowaki ,  Kazutoshi Ito ,  Toshiaki Ishii ,  Katsuo Arai ,  Takuya Nakajo ,  Hidemasa Kagii

IPC分类号： H01L23/15

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/8392 ,  H01L2224/83951 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/05432 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2924/3512 ,  H01L2224/48744

摘要： In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

摘要翻译： 在半导体器件的结构中，Si芯片和金属引线框通过金属接合，通过具有三维网状结构的高导电性金属的多孔接合层，使用Ag作为接合材料，以及含有 在与聚合物树脂接触的半导体组件的表面上形成氧化锌或氧化铝。 以这种方式，通过与主要由Ag形成的多孔结构的接合层的接合，可以降低Si片的热应力负荷，并且可以提高接合层本身的疲劳寿命。 此外，由于通过锚固效应可以提高聚合物树脂对膜的粘附性，可以防止接合部发生裂纹，从而可以提供高可靠性的无铅半导体器件。

公开(公告)号：US20120289001A1

公开(公告)日：2012-11-15

申请号：US13560786

申请日：2012-07-27

申请人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L21/60

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 制造焊料顶部器件的方法包括将顶部金属层光刻地图案化成接触区域和接触增强区域; 然后使用用于增加的复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US08203219B2

公开(公告)日：2012-06-19

申请号：US12294211

申请日：2007-03-23

申请人： Chris Wyland

发明人： Chris Wyland

IPC分类号： H01L23/48 ,  H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49558 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/91 ,  H01L2223/6611 ,  H01L2224/24226 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49175 ,  H01L2224/73277 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/01004 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Consistent with an example embodiment, there is an integrated circuit (IC) device in a packaging having electrically insulated connections. The IC device comprises a semiconductor device (100) mounted onto a die attachment area (10); the semiconductor device has a plurality of bonding pads (20a, 25a, 30a, 35a). A lead frame having a plurality of bonding fingers (20b, 25b, 30b, 35b) surrounds the die attachment area. A plurality of mutually isolated connection conductors (25d, 30d, 40, 50) having respective first ends are attached to respective bonding pads on the semiconductor device and the plurality of mutually isolated connection conductors having respective second respective second ends are attached to respective bonding fingers of the lead frame. An insulating material (45) coats at least a portion of the plurality of mutually isolated connection conductors. The mutually isolated connection conductors may include a bond wire (40, 50) for the signal connection and a conductive strap (25d, 30d) for the voltage reference connection. The insulating material (45) coating the bond wires reduces the likelihood of short circuits during encapsulation.

摘要翻译： 与示例性实施例一致，在具有电绝缘连接的封装中存在集成电路（IC）装置。 IC器件包括安装在管芯附接区域（10）上的半导体器件（100）。 半导体器件具有多个接合焊盘（20a，25a，30a，35a）。 具有多个接合指（20b，25b，30b，35b）的引线框围绕管芯附接区域。 具有各自的第一端的多个相互隔离的连接导体（25d，30d，40,50）附接到半导体器件上的各个焊盘，并且具有各自的第二相应的第二端的多个相互隔离的连接导体被附接到相应的接合指 的引线框架。 绝缘材料（45）涂覆多个相互隔离的连接导体的至少一部分。 相互隔离的连接导体可以包括用于信号连接的接合线（40,50）和用于电压参考连接的导电带（25d，30d）。 涂覆接合线的绝缘材料（45）降低了封装期间短路的可能性。

公开(公告)号：US08183684B2

公开(公告)日：2012-05-22

申请号：US12532321

申请日：2007-09-27

申请人： Isao Nakazato

发明人： Isao Nakazato

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48511 ,  H01L2224/48599 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85423 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Provided is a thin semiconductor device using a thin metal wire and having a low top portion. The semiconductor device of the present invention has a structure in which a bonding pad 55 of a semiconductor chip 54 and an electrode 53B are connected to each other via a thin metal wire 51, and the thin metal wire 51 forms a curve portion 57. Specifically, the thin metal wire 51 exhibits the curve portion 57 from a first bond, and is provided with a linear second extending portion 60 with an end portion thereof being a first bend portion 59. A second bend portion 61 is located lower than a top portion 58 of the curve portion 57.

摘要翻译： 提供一种使用细金属丝并具有低顶部的薄半导体器件。 本发明的半导体装置具有半导体芯片54的接合焊盘55和电极53B经由薄金属线51彼此连接的结构，并且金属细线51形成曲线部分57.具体地， ，细金属丝51从第一接合处呈现弯曲部分57，并且设置有线性第二延伸部分60，其端部是第一弯曲部分59.第二弯曲部分61位于比顶部部分 58的曲线部分57。

公开(公告)号：US20120091568A1

公开(公告)日：2012-04-19

申请号：US13333086

申请日：2011-12-21

申请人： Jenny Ong Wai Lian ,  Chen Wei Adrian Chng

发明人： Jenny Ong Wai Lian ,  Chen Wei Adrian Chng

IPC分类号： H01L23/495

CPC分类号： H01L23/4952 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48458 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48491 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/4554

摘要： One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plurality of first bond wires, incoluding a first electrically conductive material, extend between the chip contact pads and the plurality of first leadfingers. A plurality of second bond wires, including a second electrically conductive material, extend between a chip contact pad and a second leadfinger. The semiconductor package further includes a plurality of electrically conducting means attached to the second leadfingers.

摘要翻译： 一个实施例包括封装的半导体封装，其具有引线框架，引线框架具有由多个第一引线脚和第二引线引脚围绕的管芯焊盘。 包括其上活性表面上的芯片接触焊盘的半导体芯片附接到管芯焊盘。 浸入第一导电材料的多个第一接合线在芯片接触焊盘和多个第一引线管之间延伸。 包括第二导电材料的多个第二接合线在芯片接触焊盘和第二引线框之间延伸。 半导体封装还包括附接到第二引线管的多个导电装置。