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    Source and body contact structure for trench-DMOS devices using polysilicon
    5.
    发明授权
    Source and body contact structure for trench-DMOS devices using polysilicon 有权
    使用多晶硅的沟槽DMOS器件的源和体接触结构

    公开(公告)号：US08703563B2

    公开(公告)日：2014-04-22

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
    6.
    发明申请
    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 有权
    使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构

    公开(公告)号：US20120286356A1

    公开(公告)日：2012-11-15

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    High power and high temperature semiconductor power devices protected by non-uniform ballasted sources
    7.
    发明授权
    High power and high temperature semiconductor power devices protected by non-uniform ballasted sources 有权
    由不均匀的压载源保护的大功率和高温半导体功率器件

    公开(公告)号：US08110472B2

    公开(公告)日：2012-02-07

    申请号：US13199251

    申请日：2011-08-23

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L29/7802 ,  H01L24/05 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/7803 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.

    摘要翻译： 半导体功率器件形成在半导体衬底上。 半导体功率器件包括分布在不同区域上的多个晶体管单元，其具有取决于每个不同区域中的局部散热的不同量的镇流电阻。 示例性实施例具有在周边区域附近形成的具有较低的镇流电阻的晶体管电池，并且在接合焊盘区域附近形成具有较高耐压电性的晶体管电池。 另一个示例性实施例包括形成在引线焊盘周围的区域中具有最高镇流电阻的电池，具有较低电阻的晶体管单元形成在连接到用于散热的接合线的引线接合焊盘下方，并且具有最低的晶体管电池 在距离接合焊盘的区域中形成耐压性。

    Inverted-trench grounded-source FET structure with trenched source body short electrode
    8.
    发明授权
    Inverted-trench grounded-source FET structure with trenched source body short electrode 有权
    反沟槽接地源FET结构，具有沟槽源体短路电极

    公开(公告)号：US08008716B2

    公开(公告)日：2011-08-30

    申请号：US11522669

    申请日：2006-09-17

    申请人： Sik K Lui ,  François Hébert ,  Anup Bhalla

    发明人： Sik K Lui ,  François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/66

    CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

    摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

    Device structure and manufacturing method using HDP deposited using deposited source-body implant block
    9.
    发明申请
    Device structure and manufacturing method using HDP deposited using deposited source-body implant block 有权
    使用沉积源体植入块沉积的HDP的装置结构和制造方法

    公开(公告)号：US20120018793A1

    公开(公告)日：2012-01-26

    申请号：US13200869

    申请日：2011-10-04

    申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

    发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/788

    CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

    摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

    摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。