公开(公告)号：US09818834B2

公开(公告)日：2017-11-14

申请号：US14990009

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Ping Liu ,  Hung-Chang Hsu ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Rueijer Lin ,  Sheng-Hsuan Lin ,  Ya-Lien Lee ,  Yen-Shou Kao

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/45 ,  H01L21/768 ,  H01L29/51

CPC classification number: H01L29/456 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76856 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.

公开(公告)号：US12218012B2

公开(公告)日：2025-02-04

申请号：US18360478

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yip Loh ,  Yan-Ming Tsai ,  Hung-Hsu Chen ,  Chih-Wei Chang ,  Sheng-Hsuan Lin

IPC: H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/78

Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.

公开(公告)号：US20220277997A1

公开(公告)日：2022-09-01

申请号：US17664495

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Chen ,  Sheng-Hsuan Lin ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

公开(公告)号：US11195791B2

公开(公告)日：2021-12-07

申请号：US16707301

申请日：2019-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Wen Cheng ,  Wei-Yip Loh ,  Yu-Hsiang Liao ,  Sheng-Hsuan Lin ,  Hong-Mao Lee ,  Chun-I Tsai ,  Ken-Yu Chang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.

公开(公告)号：US20200152763A1

公开(公告)日：2020-05-14

申请号：US16740881

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/326 ,  H01L29/45

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US12191199B2

公开(公告)日：2025-01-07

申请号：US17216444

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei Chou ,  Ken-Yu Chang ,  Sheng-Hsuan Lin ,  Yueh-Ching Pai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/52 ,  H01L29/40

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20240355740A1

公开(公告)日：2024-10-24

申请号：US18345303

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Yu Chang ,  Sheng-Hsuan Lin ,  Shu-Lan Chang ,  Kai-Yi Chu ,  Meng-Hsien Lin ,  Pei-Hsuan Lee ,  Pei Shan Chang ,  Chih-Chien Chi ,  Chun-I Tsai ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/53266 ,  H01L21/7684 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.

公开(公告)号：US11810826B2

公开(公告)日：2023-11-07

申请号：US17827355

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yip Loh ,  Yan-Ming Tsai ,  Hung-Hsu Chen ,  Chih-Wei Chang ,  Sheng-Hsuan Lin

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/266 ,  H01L29/78 ,  H01L21/3213

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32135 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.

公开(公告)号：US20220367667A1

公开(公告)日：2022-11-17

申请号：US17869521

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.