公开(公告)号：US10707114B2

公开(公告)日：2020-07-07

申请号：US16049520

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Bing-Hung Chen ,  Chien-Hsun Wang ,  Cheng-Tung Lin ,  Chih-Tang Peng ,  De-Fang Chen ,  Huan-Just Lin ,  Li-Ting Wang ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US09412836B2

公开(公告)日：2016-08-09

申请号：US14198841

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Hung-Ta Lin ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/36 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/365 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.

Abstract translation: 本发明涉及一种半导体器件，其具有在晶体管的源极/漏极区域内的δ掺杂片层，以降低接触电阻，以及相关联的方法。 在一些实施例中，介电层设置在晶体管的上方。 沟槽通过电介质层设置到源极/漏极区域，并且导电接触件设置在沟槽中。 源极/漏极区域包括掺杂浓度高于源极/漏极区域的掺杂浓度的δ掺杂片层。

公开(公告)号：US11411094B2

公开(公告)日：2022-08-09

申请号：US16740881

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US11056486B2

公开(公告)日：2021-07-06

申请号：US16368827

申请日：2019-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  De-Fang Chen ,  Hui-Cheng Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.

公开(公告)号：US09853102B2

公开(公告)日：2017-12-26

申请号：US14455598

申请日：2014-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Li-Ting Wang ,  Cheng-Tung Lin ,  De-Fang Chen ,  Chih-Tang Peng ,  Chien-Hsun Wang ,  Hung-Ta Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265 ,  H01L29/51 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/16

CPC classification number: H01L29/105 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827

Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

公开(公告)号：US11227788B2

公开(公告)日：2022-01-18

申请号：US16921015

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Bing-Hung Chen ,  Chien-Hsun Wang ,  Cheng-Tung Lin ,  Chih-Tang Peng ,  De-Fang Chen ,  Huan-Just Lin ,  Li-Ting Wang ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US10535748B2

公开(公告)日：2020-01-14

申请号：US15909838

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US20150255575A1

公开(公告)日：2015-09-10

申请号：US14198841

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Hung-Ta Lin ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/365 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.

Abstract translation: 本发明涉及一种半导体器件，其具有在晶体管的源极/漏极区域内的δ掺杂片层，以降低接触电阻，以及相关联的方法。 在一些实施例中，介电层设置在晶体管的上方。 沟槽通过电介质层设置到源极/漏极区域，并且导电接触件设置在沟槽中。 源极/漏极区域包括掺杂浓度高于源极/漏极区域的掺杂浓度的δ掺杂片层。

公开(公告)号：US20220367667A1

公开(公告)日：2022-11-17

申请号：US17869521

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US10658234B2

公开(公告)日：2020-05-19

申请号：US15223902

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Sung-Li Wang ,  Pei-Wen Wu ,  Yida Li ,  Chih-Wei Chang ,  Huang-Yi Huang ,  Cheng-Tung Lin ,  Jyh-Cherng Sheu ,  Yee-Chia Yeo ,  Chi-On Chui

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L21/285 ,  H01L23/532

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.