公开(公告)号：US09853102B2

公开(公告)日：2017-12-26

申请号：US14455598

申请日：2014-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Li-Ting Wang ,  Cheng-Tung Lin ,  De-Fang Chen ,  Chih-Tang Peng ,  Chien-Hsun Wang ,  Hung-Ta Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265 ,  H01L29/51 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/16

CPC classification number: H01L29/105 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827

Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

公开(公告)号：US09412836B2

公开(公告)日：2016-08-09

申请号：US14198841

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Hung-Ta Lin ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/36 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/365 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.

Abstract translation: 本发明涉及一种半导体器件，其具有在晶体管的源极/漏极区域内的δ掺杂片层，以降低接触电阻，以及相关联的方法。 在一些实施例中，介电层设置在晶体管的上方。 沟槽通过电介质层设置到源极/漏极区域，并且导电接触件设置在沟槽中。 源极/漏极区域包括掺杂浓度高于源极/漏极区域的掺杂浓度的δ掺杂片层。

公开(公告)号：US09941394B2

公开(公告)日：2018-04-10

申请号：US14460214

申请日：2014-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Cheng-Tung Lin ,  Li-Ting Wang ,  Chih-Tang Peng ,  De-Fang Chen ,  Hung-Ta Lin ,  Chien-Hsun Wang

IPC: H01L29/06 ,  H01L29/739 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/16

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/7827

Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.

公开(公告)号：US20150255575A1

公开(公告)日：2015-09-10

申请号：US14198841

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Hung-Ta Lin ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/365 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.

Abstract translation: 本发明涉及一种半导体器件，其具有在晶体管的源极/漏极区域内的δ掺杂片层，以降低接触电阻，以及相关联的方法。 在一些实施例中，介电层设置在晶体管的上方。 沟槽通过电介质层设置到源极/漏极区域，并且导电接触件设置在沟槽中。 源极/漏极区域包括掺杂浓度高于源极/漏极区域的掺杂浓度的δ掺杂片层。