公开(公告)号：US11742240B2

公开(公告)日：2023-08-29

申请号：US17676638

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Yu-Ming Huang ,  Ethan Tseng ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L29/04 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76856 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

公开(公告)号：US20220367662A1

公开(公告)日：2022-11-17

申请号：US17876313

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US11195791B2

公开(公告)日：2021-12-07

申请号：US16707301

申请日：2019-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Wen Cheng ,  Wei-Yip Loh ,  Yu-Hsiang Liao ,  Sheng-Hsuan Lin ,  Hong-Mao Lee ,  Chun-I Tsai ,  Ken-Yu Chang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.

公开(公告)号：US12148659B2

公开(公告)日：2024-11-19

申请号：US18308743

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/8234 ,  H01L29/66

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US11955329B2

公开(公告)日：2024-04-09

申请号：US18309298

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Chun-I Tsai ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/02068 ,  H01L21/76871 ,  H01L21/76877

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

公开(公告)号：US20230268228A1

公开(公告)日：2023-08-24

申请号：US18308743

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67

CPC classification number: H01L21/76846 ,  H01L21/67075 ,  H01L21/76877 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/66545

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US20210343590A1

公开(公告)日：2021-11-04

申请号：US17372671

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/8234 ,  H01L29/66

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US20190164824A1

公开(公告)日：2019-05-30

申请号：US16203918

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3213

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US08962473B2

公开(公告)日：2015-02-24

申请号：US13833794

申请日：2013-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Shiang Kuo ,  Ken-Yu Chang ,  Ya-Lien Lee ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底之上的电介质层的内部形成有开口。 开口有一堵墙。 然后通过至少两个交替的步骤在开口的壁上形成至少一个扩散阻挡材料，所述至少两个交替步骤选自由物理气相沉积（PVD）和原子层沉积（ALD）的过程组成的组。 衬里层形成在至少一个扩散阻挡材料上。

公开(公告)号：US12191199B2

公开(公告)日：2025-01-07

申请号：US17216444

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei Chou ,  Ken-Yu Chang ,  Sheng-Hsuan Lin ,  Yueh-Ching Pai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/52 ,  H01L29/40

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.