公开(公告)号：US20240413020A1

公开(公告)日：2024-12-12

申请号：US18488393

申请日：2023-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chun-I Tsai ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo ,  Wei-Jung Lin ,  Yu-Ting Wen ,  Kai-Chieh Yang

IPC: H01L21/8238 ,  H01L21/321 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

公开(公告)号：US20240387265A1

公开(公告)日：2024-11-21

申请号：US18786535

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US20240136227A1

公开(公告)日：2024-04-25

申请号：US18402859

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Chen ,  Sheng-Hsuan Lin ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/02123 ,  H01L21/02269 ,  H01L21/02274 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

公开(公告)号：US11901229B2

公开(公告)日：2024-02-13

申请号：US17664495

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Chen ,  Sheng-Hsuan Lin ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/76897 ,  H01L21/02123 ,  H01L21/02269 ,  H01L21/02274 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

公开(公告)号：US11854874B2

公开(公告)日：2023-12-26

申请号：US17086754

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522

CPC classification number: H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US20230260836A1

公开(公告)日：2023-08-17

申请号：US17663315

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei Shan Chang ,  Yi-Hsiang Chao ,  Chun-Hsien Huang ,  Peng-Hao Hsu ,  Kevin Lee ,  Shu-Lan Chang ,  Ya-Yi Cheng ,  Ching-Yi Chen ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/76852 ,  H01L29/78618 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823418 ,  H01L21/76876

Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

公开(公告)号：US20220376111A1

公开(公告)日：2022-11-24

申请号：US17484039

申请日：2021-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju Lin ,  Chien Chang ,  Chih-Shiun Chou ,  TaiMin Chang ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Lin-Yu Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

公开(公告)号：US20220352020A1

公开(公告)日：2022-11-03

申请号：US17809922

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  I-Li Chen ,  Pin-Wen Chen ,  Yuan-Chen Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening

公开(公告)号：US11011611B2

公开(公告)日：2021-05-18

申请号：US16914638

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Yi-Hsiang Chao ,  Kuan-Yu Yeh ,  Kan-Ju Lin ,  Chun-Wen Nieh ,  Huang-Yi Huang ,  Chih-Wei Chang ,  Ching-Hwanq Su

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/306 ,  H01L29/08

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a conductive region made of silicon, germanium or a combination thereof. The semiconductor device structure also includes an insulating layer over the semiconductor substrate and a fill metal material layer in the insulating layer. In addition, the semiconductor device structure includes a nitrogen-containing metal silicide or germanide layer between the conductive region and the fill metal material layers.

公开(公告)号：US10475702B2

公开(公告)日：2019-11-12

申请号：US15920727

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Chih-Wei Chang ,  Mei-Hui Fu ,  Ming-Hsing Tsai ,  Wei-Jung Lin ,  Yu Shih Wang ,  Ya-Yi Cheng ,  I-Li Chen

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/3213 ,  H01L21/285

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.