公开(公告)号：US20230223302A1

公开(公告)日：2023-07-13

申请号：US17663302

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L23/535 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76889

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US20210118748A1

公开(公告)日：2021-04-22

申请号：US17113431

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hsiu Perng ,  Kai-Chieh Yang ,  Zhi-Chang Lin ,  Teng-Chun Tsai ,  Wei-Hao Wu

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  C23C16/04 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

公开(公告)号：US20160064541A1

公开(公告)日：2016-03-03

申请号：US14473215

申请日：2014-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. DIAZ ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Kai-Chieh Yang ,  Hao-Ling Tang

IPC: H01L29/778 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7843

Abstract: A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

Abstract translation: 垂直晶体管包括源极 - 沟道 - 漏极结构，栅极和栅极电介质层。 源极 - 沟道 - 漏极结构包括源极，源极上的漏极和源极和漏极之间的沟道。 门围绕通道的一部分。 栅极被配置为当垂直晶体管是n沟道垂直晶体管时，基本沿着沟道的延伸方向提供压缩应变，或者当垂直晶体管为垂直晶体管时，栅极被配置为基本上沿着沟道的延伸方向提供拉伸应变 一个p沟道垂直晶体管。 在一些实施例中，垂直晶体管还包括ILD，其被配置为当垂直晶体管是n沟道垂直晶体管时基本上沿着沟道的延伸方向提供拉伸应变，或者构造成基本上沿着沟道的延伸方向提供压缩应变 当垂直晶体管是p沟道垂直晶体管时。

公开(公告)号：US20250095997A1

公开(公告)日：2025-03-20

申请号：US18601167

申请日：2024-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Kuan-Kan Hu ,  Wei-Yen Woon ,  Ku-Feng Yang ,  Szuya Liao

IPC: H01L21/28 ,  H01L21/822 ,  H01L27/12 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.

公开(公告)号：US12148830B2

公开(公告)日：2024-11-19

申请号：US18324405

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Wei Ju Lee ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US11545400B2

公开(公告)日：2023-01-03

申请号：US17113431

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hsiu Perng ,  Kai-Chieh Yang ,  Zhi-Chang Lin ,  Teng-Chun Tsai ,  Wei-Hao Wu

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  C23C16/04 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

公开(公告)号：US11532519B2

公开(公告)日：2022-12-20

申请号：US17340660

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/092

Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

公开(公告)号：US20190259862A1

公开(公告)日：2019-08-22

申请号：US16404239

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lun Cheng ,  Li-Shyue Lai ,  Ching-Wei Tsai ,  Kai-Chieh Yang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423 ,  H01L29/40 ,  H01L21/311

Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.

公开(公告)号：US20240105850A1

公开(公告)日：2024-03-28

申请号：US18521794

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

公开(公告)号：US11664451B2

公开(公告)日：2023-05-30

申请号：US17216241

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Wei Ju Lee ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.