公开(公告)号：US20220359223A1

公开(公告)日：2022-11-10

申请号：US17869150

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L21/321 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US11367658B2

公开(公告)日：2022-06-21

申请号：US16933676

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen

IPC: H01L21/82 ,  H01L23/00 ,  H01L21/268 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.

公开(公告)号：US20200303275A1

公开(公告)日：2020-09-24

申请号：US16895415

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Lin Huang ,  Jung-Hua Chang ,  Jy-Jie Gau ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.

公开(公告)号：US10014218B1

公开(公告)日：2018-07-03

申请号：US15492525

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fu Shih ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Che-Jung Chu ,  Wen-Ming Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/5446 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L21/304

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.

公开(公告)号：US09870975B1

公开(公告)日：2018-01-16

申请号：US15210343

申请日：2016-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hua Wang ,  Po-Yao Lin ,  Shu-Shen Yeh ,  Kuang-Chun Lee ,  Shin-Puu Jeng ,  Shyue-Ter Leu ,  Cheng-Lin Huang ,  Hsiu-Mei Yu

IPC: H01L23/34 ,  H01L23/373 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L23/3107 ,  H01L23/3157 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/48221 ,  H01L2224/4909 ,  H01L2225/06541

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.

公开(公告)号：US09595510B1

公开(公告)日：2017-03-14

申请号：US14881840

申请日：2015-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jui-Pin Hung ,  Cheng-Lin Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/10

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/10 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83005

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

Abstract translation: 提供了芯片封装的结构和形成方法。 芯片封装包括半导体管芯和部分地或完全地封装半导体管芯的封装层。 芯片封装还包括穿透封装层的导电特性。 芯片封装进一步包括界面层，界面层连续地围绕导电特征。 界面层位于导电特征与封装层之间，界面层由金属氧化物材料制成。

公开(公告)号：US11784091B2

公开(公告)日：2023-10-10

申请号：US16893939

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Wei Li ,  Jung-Hua Chang ,  Cheng-Lin Huang

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/76885 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor die. The method further includes forming an insulating layer over the protective layer. The insulating layer has an opening exposing a portion of the conductive structure. In addition, the method includes forming a conductive layer over the insulating layer. The conductive layer fills the opening, and the conductive layer has a substantially planar top surface.

公开(公告)号：US20210066179A1

公开(公告)日：2021-03-04

申请号：US16893119

申请日：2020-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Wei Li ,  Jung-Hua Chang ,  Cheng-Lin Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

公开(公告)号：US20200373267A1

公开(公告)日：2020-11-26

申请号：US16989461

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fu Shih ,  Chun-Yen Lo ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chien-Ming Huang ,  Yuan-Fu Liu ,  Yung-Chiuan Cheng ,  Wei-Chih Huang ,  Chen-Hsun Liu ,  Chien-Pin Chan ,  Yu-Nu Hsu ,  Chi-Hung Lin ,  Te-Hsun Pang ,  Chin-Yu Ku

IPC: H01L23/00 ,  C25D5/12 ,  C25D5/50 ,  C25D7/12 ,  C25D17/00 ,  C25D17/12 ,  C25D21/10

Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

公开(公告)号：US10770427B1

公开(公告)日：2020-09-08

申请号：US16454435

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Wei Li ,  Jung-Hua Chang ,  Cheng-Lin Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/482

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive via structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer over a second surface of the first substrate. The method includes forming a first insulating layer over the barrier layer. The method includes forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad continuously extends from the conductive via structure into the third opening. The method includes forming a conductive bump over the conductive pad in the third opening.