公开(公告)号：US20170221910A1

公开(公告)日：2017-08-03

申请号：US15008748

申请日：2016-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Lin Chen ,  Shyh-Wei Cheng ,  Che-Jung Chu

IPC: H01L27/115 ,  G11C16/04 ,  H01L21/28

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C17/08 ,  H01L21/28273 ,  H01L27/11524

Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided

公开(公告)号：US11088108B2

公开(公告)日：2021-08-10

申请号：US16454350

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yao Yang ,  Ling-Wei Li ,  Yu-Jui Wu ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Lieh-Chuan Chen ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

公开(公告)号：US10170429B2

公开(公告)日：2019-01-01

申请号：US15431802

申请日：2017-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Chi Huang ,  Chien-Chen Li ,  Kuo-Lung Li ,  Cheng-Liang Cho ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H01L21/683

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package component including a first bump. The package structure also includes an intermetallic compound (IMC) on the first bump. The package structure further includes an integrated circuit die including a second bump on the IMC. The integrated circuit die and the package component are bonded together through the first bump and the second bump. The IMC extends from the first bump to the second bump to provide good physical and electrical connections between the first bump and the second bump.

公开(公告)号：US09865609B2

公开(公告)日：2018-01-09

申请号：US15008748

申请日：2016-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Lin Chen ,  Shyh-Wei Cheng ,  Che-Jung Chu

IPC: H01L27/115 ,  H01L21/28 ,  H01L27/11521 ,  G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C17/08 ,  H01L21/28273 ,  H01L27/11524

Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.

公开(公告)号：US10014218B1

公开(公告)日：2018-07-03

申请号：US15492525

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fu Shih ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Che-Jung Chu ,  Wen-Ming Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/5446 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L21/304

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.