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公开(公告)号：US20220238480A1
公开(公告)日：2022-07-28
申请号：US17347871
申请日：2021-06-15
发明人： Kai Jun Zhan , Chin-Fu Kao , Kuang-Chun Lee , Ming-Da Cheng , Chen-Shien Chen
IPC分类号： H01L23/00
摘要： A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.
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公开(公告)号：US10276551B2
公开(公告)日：2019-04-30
申请号：US15854762
申请日：2017-12-27
发明人： Po-Yao Lin , Cheng-Yi Hong , Feng-Cheng Hsu , Shuo-Mao Chen , Shin-Puu Jeng , Shu-Shen Yeh , Kuang-Chun Lee
IPC分类号： H01L23/053 , H01L23/12 , H01L25/18 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/24 , H01L25/00 , H01L23/31 , H01L23/373
摘要： A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
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公开(公告)号：US20230411307A1
公开(公告)日：2023-12-21
申请号：US17841275
申请日：2022-06-15
发明人： Wen-Yi Lin , Kuang-Chun Lee , Chien-Chen Li , Chien-Li Kuo , Kuo-Chio Liu
IPC分类号： H01L23/00 , H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56
CPC分类号： H01L23/562 , H01L23/3185 , H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L21/563
摘要： Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.
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公开(公告)号：US20230377905A1
公开(公告)日：2023-11-23
申请号：US17751234
申请日：2022-05-23
发明人： Chien-Li Kuo , Chien-Chen Li , Kuo-Chio Liu , Kuang-Chun Lee , Wen-Yi Lin
IPC分类号： H01L21/48 , H01L23/48 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/00
CPC分类号： H01L21/486 , H01L23/481 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/73 , H01L2224/04105 , H01L2224/12105 , H01L2924/15311 , H01L2224/73267
摘要： In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.
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公开(公告)号：US11508710B2
公开(公告)日：2022-11-22
申请号：US16884046
申请日：2020-05-27
发明人： Po-Yao Lin , Cheng-Yi Hong , Feng-Cheng Hsu , Shuo-Mao Chen , Shin-Puu Jeng , Shu-Shen Yeh , Kuang-Chun Lee
IPC分类号： H01L25/18 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/24 , H01L25/00 , H01L23/31 , H01L21/683 , H01L23/00 , H01L23/373
摘要： A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
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公开(公告)号：US10163816B2
公开(公告)日：2018-12-25
申请号：US15180404
申请日：2016-06-13
发明人： Shu-Shen Yeh , Chin-Hua Wang , Kuang-Chun Lee , Po-Yao Lin , Shyue-Ter Leu , Shin-Puu Jeng
IPC分类号： H01L23/10 , H01L23/04 , H01L23/00 , H01L23/498 , H01L23/367
摘要： Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and the lid has one or more openings between two of the support structures.
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公开(公告)号：US09748156B1
公开(公告)日：2017-08-29
申请号：US15180264
申请日：2016-06-13
发明人： Shu-Shen Yeh , Cheng-Lin Huang , Chin-Hua Wang , Kuang-Chun Lee , Wen-Yi Lin , Ming-Chih Yew , Yu-Huan Chen , Po-Yao Lin , Shyue-Ter Leu , Shin-Puu Jeng
CPC分类号： H01L23/18 , H01L23/16 , H01L23/3128 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2224/48091 , H01L2225/1058 , H01L2225/1076 , H01L2924/00014
摘要： A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.
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公开(公告)号：US20240071950A1
公开(公告)日：2024-02-29
申请号：US17898075
申请日：2022-08-29
发明人： Wen-Yi Lin , Kuang-Chun Lee , Chien-Chen Li , Chien-Li Kuo , Kuo-Chio Liu
IPC分类号： H01L23/00 , H01L21/48 , H01L21/56 , H01L23/498
CPC分类号： H01L23/562 , H01L21/4817 , H01L21/563 , H01L23/49816 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16221 , H01L2224/32225 , H01L2224/73204 , H01L2924/3511 , H01L2924/3512 , H01L2924/37001
摘要： Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.
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公开(公告)号：US10797006B2
公开(公告)日：2020-10-06
申请号：US16200838
申请日：2018-11-27
发明人： Shu-Shen Yeh , Chin-Hua Wang , Kuang-Chun Lee , Po-Yao Lin , Shyue-Ter Leu , Shin-Puu Jeng
IPC分类号： H01L23/00 , H01L23/367 , H01L23/04 , H01L23/10 , H01L23/498
摘要： Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has multiple support structures, and the support structures are positioned at respective corner portions of the substrate. Multiple openings penetrate through the lid to expose a space containing the semiconductor die.
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公开(公告)号：US10714463B2
公开(公告)日：2020-07-14
申请号：US16693337
申请日：2019-11-24
发明人： Po-Yao Lin , Cheng-Yi Hong , Feng-Cheng Hsu , Shuo-Mao Chen , Shin-Puu Jeng , Shu-Shen Yeh , Kuang-Chun Lee
IPC分类号： H01L23/053 , H01L23/12 , H01L25/18 , H01L21/48 , H01L21/56 , H01L23/24 , H01L25/00 , H01L23/31 , H01L21/683 , H01L23/00 , H01L23/538 , H01L23/373
摘要： A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
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