公开(公告)号：US09331176B2

公开(公告)日：2016-05-03

申请号：US13870471

申请日：2013-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Dong-Won Kim

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7856

Abstract: Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin.

Abstract translation: 提供了形成鳍状场效应晶体管（FinFET）的方法。 所述方法可以包括使用掩模来将源极/漏极延伸区掺杂物选择性地并入到半导体鳍片的源极和漏极区域中，以阻止源极/漏极延伸区掺杂物掺入到半导体鳍片的至少部分中。 所述方法可以包括去除半导体鳍片的源区和漏区的部分以在其中限定凹陷。 所述方法可以包括从半导体鳍片中的凹部外延生长源极和漏极区域。

公开(公告)号：US20150325683A1

公开(公告)日：2015-11-12

申请号：US14612797

申请日：2015-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Hwi Cho ,  Dong-Won Kim ,  Yoshinao Harada ,  Myung-Gil Kang ,  Jae-Young Park

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/66803 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate is performed to form a fixed charge region including a fixed charge at a surface of the substrate. A MOS transistor is formed on the substrate including the fixed charge region. By the above processes, the threshold voltage of the MOS transistor may be easily controlled.

Abstract translation: 在制造半导体器件的方法中，执行等离子体退火并将阈值电压控制气体供应到衬底的一部分上，以在衬底的表面上形成包括固定电荷的固定电荷区域。 在包括固定电荷区的基板上形成MOS晶体管。 通过上述处理，可以容易地控制MOS晶体管的阈值电压。

公开(公告)号：US08815702B2

公开(公告)日：2014-08-26

申请号：US13854322

申请日：2013-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Ming Li ,  Sung-Hwan Kim

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Abstract translation: 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US08753945B2

公开(公告)日：2014-06-17

申请号：US13687104

申请日：2012-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keon-Yong Cheon ,  Dong-Won Kim ,  Sung-Man Lim ,  Sadaaki Masuoka ,  Yaoqi Dong

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.

Abstract translation: 在形成MOS晶体管的方法中，在衬底上形成栅极结构，并且在与栅极结构一致的衬底上形成第一间隔层。 在第一间隔层上形成第二间隔层。 通过从第一间隔层部分去除第二间隔层，在对应于栅极结构的侧壁的第一间隔层上形成第二间隔物。 通过使用包括第一间隔层和第二间隔物的栅极结构作为离子注入掩模的离子注入工艺将杂质注入到衬底中，以在栅极结构周围的衬底的表面部分处形成源极/漏极延伸区域。

公开(公告)号：US09461132B2

公开(公告)日：2016-10-04

申请号：US14511193

申请日：2014-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keon-Yong Cheon ,  Il-Ryong Kim ,  Dong-Won Kim

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/42372 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: Provided is a semiconductor device having mid-gap work function metal gate electrodes. The semiconductor device includes a plurality of gate patterns, and the gate patterns have different gate electrode metals from each other or different gate electrode metal thicknesses from each other.

Abstract translation: 提供了具有中间功函数金属栅电极的半导体器件。 半导体器件包括多个栅极图案，并且栅极图案具有彼此不同的栅电极金属或彼此不同的栅电极金属厚度。

公开(公告)号：US20150225888A1

公开(公告)日：2015-08-13

申请号：US14620087

申请日：2015-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim

IPC: D06F39/10

CPC classification number: D06F39/10 ,  D06F39/12

Abstract: A washing machine is provided that includes a cabinet and a tub disposed in the cabinet and configured to receive washing water. The washing machine includes a pump filter configured to filter foreign substances from the washing water received from the tub, a pump filter housing configured to receive the pump filter, a housing cover configured to open and close the pump filter housing, and at least one coupling portion extending from the housing cover and at least a portion of the at least one coupling portion being coupled to the pump filter housing. The washing machine further includes rails disposed on the pump filter housing, the rails being configured to receive the at least one coupling portion, and the rails being configured to allow movement of the at least one coupling portion as a function of whether the housing cover is in an open state or a closed state.

Abstract translation: 提供了一种洗衣机，其包括设置在机柜中并构造成接收洗涤水的机柜和浴缸。 所述洗衣机包括：泵过滤器，被配置为从从所述桶接收的洗涤水中过滤异物;泵过滤器壳体，构造成接纳所述泵过滤器;壳体盖，其构造成打开和关闭所述泵过滤器壳体;以及至少一个联接器 所述部分从所述壳体盖延伸并且所述至少一个联接部分的至少一部分联接到所述泵过滤器壳体。 洗衣机还包括设置在泵过滤器壳体上的轨道，轨道被配置为容纳至少一个联接部分，并且轨道构造成允许至少一个联接部分的移动，作为壳体盖是否为 处于打开状态或关闭状态。

公开(公告)号：US08748239B2

公开(公告)日：2014-06-10

申请号：US13956482

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Kim ,  Young-Goan Jang ,  Dong-Won Kim ,  Hag-Ju Cho

IPC: H01L21/335 ,  H01L21/8232

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Abstract translation: 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。

公开(公告)号：USRE49988E1

公开(公告)日：2024-05-28

申请号：US17569902

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/775 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US11784255B2

公开(公告)日：2023-10-10

申请号：US17119507

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan Yu ,  Sung-Min Kim ,  Dong-Suk Shin ,  Seung-Hun Lee ,  Dong-Won Kim

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H10B10/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H10B10/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

公开(公告)号：US20180138188A1

公开(公告)日：2018-05-17

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L27/11534 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L27/11524

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.