公开(公告)号：US20240324205A1

公开(公告)日：2024-09-26

申请号：US18469705

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan Kang ,  Jae-Hwang Sim

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A 3D semiconductor memory device includes a source structure, a gate stack structure disposed on the source structure and comprising insulating patterns and conductive patterns which are alternately stacked, a through-plug, a pad in contact with the through-plug, and a pad insulating pattern under the pad. The conductive patterns include a selection conductive line in contact with the through-plug. The through-plug includes an extension plug portion and a parallel plug portion. A height of the pad is less than a height of the conductive pattern.

公开(公告)号：US10593689B2

公开(公告)日：2020-03-17

申请号：US15685650

申请日：2017-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/11526

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

公开(公告)号：US20170373085A1

公开(公告)日：2017-12-28

申请号：US15685650

申请日：2017-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L27/11573 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11526 ,  H01L21/033

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11526

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

公开(公告)号：US08829644B2

公开(公告)日：2014-09-09

申请号：US14072250

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

IPC: H01L21/70 ,  H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract translation: 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

公开(公告)号：US10083978B2

公开(公告)日：2018-09-25

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/1157 ,  H01L27/11534 ,  H01L27/11524 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  Y02E10/50

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US20180061843A1

公开(公告)日：2018-03-01

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US09875897B2

公开(公告)日：2018-01-23

申请号：US15335190

申请日：2016-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang Sim

IPC: H01L21/033 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/06

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0649

Abstract: A semiconductor device includes line patterns extending in a first direction, and separated from each other in a second direction perpendicular to the first direction. The plurality of line patterns includes at least two line sets, and each of the line sets includes four line patterns consecutively disposed in the second direction and having a length which varies based on location, and the at least two line sets have substantially an identical length.

公开(公告)号：US09508551B2

公开(公告)日：2016-11-29

申请号：US14665141

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun Seong ,  Jae-Hwang Sim ,  Jeehoon Han

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

Abstract translation: 制造半导体器件的方法包括在衬底的第一表面上堆叠蚀刻目标层，第一掩模层和第二掩模层。 多个第一间隔线彼此平行地形成，并且形成第二掩模层上的第一间隔垫线。 形成与第二掩模层上的至少第一间隔垫线接触的第三掩模焊盘。 蚀刻第二掩模层和第一掩模层以形成一个或多个第一掩模线，第一掩模预焊垫和第二掩模图案。 分别形成覆盖第一掩模预备焊盘和第一掩模线的侧壁的第二间隔线。 形成第一掩模垫。 蚀刻目标层被蚀刻以形成连接到导线的导电线和导电焊盘。

公开(公告)号：US09461058B2

公开(公告)日：2016-10-04

申请号：US15016737

申请日：2016-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/788

CPC classification number: H01L27/11519 ,  H01L21/0214 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L27/11524 ,  H01L29/0696 ,  H01L29/6653 ,  H01L29/6656

Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成阻挡层，下硬掩模层，中间硬掩模层和上硬掩模图案，在上硬掩模图案的侧壁上形成第一间隔图案，选择性地蚀刻 使用第一间隔图案作为蚀刻掩模的中间硬掩模层，在蚀刻的中间硬掩模层的侧壁上形成第二间隔图案，使用蚀刻的第二间隔层作为蚀刻掩模选择性地蚀刻下硬掩模层，形成图案掩模 露出细胞区域并覆盖蚀刻的下部硬掩模层和阻挡层上的共同源极线区域，并且使用蚀刻的下部硬掩模层和图案化掩模图案作为蚀刻掩模选择性地蚀刻阻挡层以形成阻挡层图案 。

公开(公告)号：US20160233223A1

公开(公告)日：2016-08-11

申请号：US15016737

申请日：2016-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Sung SONG ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L27/115 ,  H01L21/311 ,  H01L29/788 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L27/11519 ,  H01L21/0214 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L27/11524 ,  H01L29/0696 ,  H01L29/6653 ,  H01L29/6656

Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成阻挡层，下硬掩模层，中间硬掩模层和上硬掩模图案，在上硬掩模图案的侧壁上形成第一间隔图案，选择性地蚀刻 使用第一间隔图案作为蚀刻掩模的中间硬掩模层，在蚀刻的中间硬掩模层的侧壁上形成第二间隔图案，使用蚀刻的第二间隔层作为蚀刻掩模选择性地蚀刻下硬掩模层，形成图案掩模 露出细胞区域并覆盖蚀刻的下部硬掩模层和阻挡层上的共同源极线区域，并且使用蚀刻的下部硬掩模层和图案化掩模图案作为蚀刻掩模选择性地蚀刻阻挡层以形成阻挡层图案 。