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    Methods of fabricating semiconductor devices including multiple patterning
    1.
    发明授权
    Methods of fabricating semiconductor devices including multiple patterning 有权
    制造包括多个图案化的半导体器件的方法

    公开(公告)号：US09461058B2

    公开(公告)日：2016-10-04

    申请号：US15016737

    申请日：2016-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

    IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/788

    CPC classification number: H01L27/11519 ,  H01L21/0214 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L27/11524 ,  H01L29/0696 ,  H01L29/6653 ,  H01L29/6656

    Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

    Abstract translation: 制造半导体器件的方法可以包括在衬底上形成阻挡层，下硬掩模层，中间硬掩模层和上硬掩模图案，在上硬掩模图案的侧壁上形成第一间隔图案，选择性地蚀刻 使用第一间隔图案作为蚀刻掩模的中间硬掩模层，在蚀刻的中间硬掩模层的侧壁上形成第二间隔图案，使用蚀刻的第二间隔层作为蚀刻掩模选择性地蚀刻下硬掩模层，形成图案掩模 露出细胞区域并覆盖蚀刻的下部硬掩模层和阻挡层上的共同源极线区域，并且使用蚀刻的下部硬掩模层和图案化掩模图案作为蚀刻掩模选择性地蚀刻阻挡层以形成阻挡层图案 。

    Nonvolatile memory device and method of manufacturing the same
    4.
    发明授权
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08829644B2

    公开(公告)日：2014-09-09

    申请号：US14072250

    申请日：2013-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

    IPC: H01L21/70 ,  H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

    Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

    Abstract translation: 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

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