公开(公告)号：US20180138188A1

公开(公告)日：2018-05-17

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L27/11534 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L27/11524

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US09905569B1

公开(公告)日：2018-02-27

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L21/8234 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US10083978B2

公开(公告)日：2018-09-25

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/1157 ,  H01L27/11534 ,  H01L27/11524 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  Y02E10/50

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US20180061843A1

公开(公告)日：2018-03-01

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.