公开(公告)号：US08815702B2

公开(公告)日：2014-08-26

申请号：US13854322

申请日：2013-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Ming Li ,  Sung-Hwan Kim

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Abstract translation: 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US09673099B2

公开(公告)日：2017-06-06

申请号：US15136450

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L21/8234 ,  H01L29/775 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US09324850B2

公开(公告)日：2016-04-26

申请号：US14162052

申请日：2014-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Abstract translation: 集成电路器件包括第一晶体管，其具有在第一源极/漏极之间的第一沟道和在第二源极/漏极之间具有第二沟道的第二晶体管。 第一晶体管基于第一电流量而工作，并且第二晶体管基于不同于第一电流量的第二电流量来操作。 第一和第二通道具有固定的通道宽度。 固定通道宽度可以基于包括在第一和第二晶体管中的翅片或纳米线。

公开(公告)号：US20140127872A1

公开(公告)日：2014-05-08

申请号：US14150006

申请日：2014-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Woo Oh ,  Sang-Hoon LEE ,  Sung-Bong KIM ,  Hyung-Suk LEE

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method of fabricating a fin field effect transistor may include forming a fin portion protruding from a substrate, forming a device isolation layer to cover a lower sidewall of the fin portion, forming a semiconductor layer using an epitaxial method to cover an upper sidewall and a top surface of the fin portion, selectively etching an upper portion of the device isolation layer to form a gap region between a top surface of the device isolation layer and a bottom surface of the semiconductor layer, and forming a gate electrode pattern on the semiconductor layer to fill the gap region. Related devices are also described.

Abstract translation: 制造鳍状场效应晶体管的方法可以包括形成从衬底突出的鳍部，形成器件隔离层以覆盖鳍部的下侧壁，使用外延法形成半导体层以覆盖上侧壁和 选择性地蚀刻器件隔离层的上部以在器件隔离层的顶表面和半导体层的底表面之间形成间隙区域，并在半导体层上形成栅电极图案 填补空白区域。 还描述了相关设备。

公开(公告)号：USRE49988E1

公开(公告)日：2024-05-28

申请号：US17569902

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/775 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US20130224925A1

公开(公告)日：2013-08-29

申请号：US13854322

申请日：2013-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Ming Li ,  Sung-Hwan Kim

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Abstract translation: 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。