公开(公告)号：US09087842B2

公开(公告)日：2015-07-21

申请号：US14304750

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon ,  Sung-Man Lim

IPC: H01L27/10 ,  H01L29/00 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.

Abstract translation: 半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。 熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。 导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。 保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。

公开(公告)号：US08753945B2

公开(公告)日：2014-06-17

申请号：US13687104

申请日：2012-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keon-Yong Cheon ,  Dong-Won Kim ,  Sung-Man Lim ,  Sadaaki Masuoka ,  Yaoqi Dong

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.

Abstract translation: 在形成MOS晶体管的方法中，在衬底上形成栅极结构，并且在与栅极结构一致的衬底上形成第一间隔层。 在第一间隔层上形成第二间隔层。 通过从第一间隔层部分去除第二间隔层，在对应于栅极结构的侧壁的第一间隔层上形成第二间隔物。 通过使用包括第一间隔层和第二间隔物的栅极结构作为离子注入掩模的离子注入工艺将杂质注入到衬底中，以在栅极结构周围的衬底的表面部分处形成源极/漏极延伸区域。