公开(公告)号：US08524554B2

公开(公告)日：2013-09-03

申请号：US13653312

申请日：2012-10-16

Applicant: IMEC ,  Samsung Electronics Co., Ltd. ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/513

Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Abstract translation: 公开了一种双功能半导体器件及其制造方法。 一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。 第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。 第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。 第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。 选择金属层以确定第一功函数。 选择第一介电覆盖层以确定第二功函数。

公开(公告)号：US08748239B2

公开(公告)日：2014-06-10

申请号：US13956482

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Kim ,  Young-Goan Jang ,  Dong-Won Kim ,  Hag-Ju Cho

IPC: H01L21/335 ,  H01L21/8232

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Abstract translation: 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。

公开(公告)号：US20130052815A1

公开(公告)日：2013-02-28

申请号：US13653312

申请日：2012-10-16

Applicant: IMEC ,  Samsung Electronics Co., Ltd. ,  Taiwan Semiconductor Manufacturing Company, L

Inventor： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

IPC: H01L21/283

CPC classification number: H01L21/823857 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/513

Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.