公开(公告)号：US09876017B2

公开(公告)日：2018-01-23

申请号：US14559258

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  G11C5/06 ,  G11C8/14 ,  G11C11/418 ,  G11C11/412 ,  G11C8/16 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

公开(公告)号：US20170207313A1

公开(公告)日：2017-07-20

申请号：US15213879

申请日：2016-07-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  Peijie Feng ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure employing recessed conductive structures for conductively coupling nanowire structures are disclosed. Conductive structures are disposed between adjacent nanowire structures to conductively couple nanowire structures. Providing conductive structures in the nanowire channel structure increases the average cross-sectional area of nanowire structures, as compared to a similar nanowire channel structure not employing conductive structures, thus increasing effective channel width and drive strength for a given channel structure height. The precision of a gate material filling process is also eased, because gate material does not have to be disposed in areas between adjacent nanowire structures occupied by conductive structures. The conductive structure width can also be recessed with regard to width of nanowire structures in the nanowire channel structure to allow for a thicker metal gate to lower the gate resistance, while providing excellent electrostatic gate control of the channel.

公开(公告)号：US09691868B2

公开(公告)日：2017-06-27

申请号：US14283168

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L29/423 ,  G03F7/20 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4238 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0886

Abstract: Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.

公开(公告)号：US20170140986A1

公开(公告)日：2017-05-18

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  G06F17/50

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

公开(公告)号：US09653399B2

公开(公告)日：2017-05-16

申请号：US14622516

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/52 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/535

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

公开(公告)号：US09536596B2

公开(公告)日：2017-01-03

申请号：US14468976

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/40 ,  G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C29/00 ,  H01L27/02 ,  H01L27/11 ,  H01L21/3213 ,  H01L21/768

CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C29/816 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/1104

Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).

Abstract translation: 一种装置包括第一读取端口，第二读取端口，写入端口和至少一个存储锁存器。 包括第一读取端口，第二读取端口和写入端口的位单元的宽度大于与位单元相关联的接触多边距（CPP）的两倍。 例如，位单元可以是与自对准双图案（SADP）工艺兼容的3端口静态随机存取存储器（SRAM）位单元，并且可以使用小于14纳米（nm）的半导体制造工艺来制造 ）。

公开(公告)号：US20160293485A1

公开(公告)日：2016-10-06

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract translation: 翅片型半导体器件包括栅极结构和源极/漏极结构。 翅片型半导体器件还包括耦合到栅极结构的栅极硬掩模结构。 门硬掩模结构包括第一材料。 翅片型半导体器件还包括耦合到源极/漏极结构的源极/漏极硬掩模结构。 源极/漏极硬掩模结构包括第二材料。

公开(公告)号：US20160163646A1

公开(公告)日：2016-06-09

申请号：US14670280

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Niladri Narayan Mojumder ,  Stanley Seungchul Song

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus includes a first fin of a first transistor and a second fin of a second transistor. The apparatus also include a first contact coupled to the first fin and a second contact coupled to the second fin. The apparatus further includes a strapped contact coupled to the first contact and to the second contact.

Abstract translation: 一种装置包括第一晶体管的第一鳍片和第二晶体管的第二鳍片。 该装置还包括耦合到第一鳍片的第一触点和耦合到第二鳍片的第二触点。 该装置还包括耦合到第一触点和第二触点的绑扎触点。

公开(公告)号：US09336863B2

公开(公告)日：2016-05-10

申请号：US14320024

申请日：2014-06-30

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

IPC: G11C11/417 ,  G11C5/06 ,  G11C7/00 ,  G11C8/16 ,  G11C5/02 ,  G11C11/419 ,  G11C11/412 ,  G11C8/14 ,  G11C7/20

CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是可以独立控制的。

公开(公告)号：US20160086805A1

公开(公告)日：2016-03-24

申请号：US14626293

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Zhongze Wang ,  Kern Rim ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/28 ,  H01L21/306 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28079 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer.

Abstract translation: 特定的半导体器件包括衬底，源极接触，漏极接触和金属栅极。 衬底包括源极区，漏极区和沟道。 源极触点耦合到源极区域。 漏极触点耦合到漏极区域。 金属栅极耦合到通道。 金属栅极包括非晶金属层。