公开(公告)号：US09941154B2

公开(公告)日：2018-04-10

申请号：US15390405

申请日：2016-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

公开(公告)号：US20180058943A1

公开(公告)日：2018-03-01

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Chidi Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L21/66 ,  H01L49/02 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  G01K7/24

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US09853112B2

公开(公告)日：2017-12-26

申请号：US14802479

申请日：2015-07-17

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/538 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/304 ,  H01L27/02

CPC classification number: H01L29/4238 ,  G06F17/5077 ,  H01L21/3043 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

公开(公告)号：US09812188B2

公开(公告)日：2017-11-07

申请号：US14631603

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Zhongze Wang ,  Xiaonan Chen ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/02 ,  G11C29/24 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

公开(公告)号：US09806083B2

公开(公告)日：2017-10-31

申请号：US14559205

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  G11C5/06 ,  G11C8/14 ,  G11C11/412 ,  H01L21/768 ,  G11C8/16 ,  G11C11/418 ,  H01L27/02

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

公开(公告)号：US20170236841A1

公开(公告)日：2017-08-17

申请号：US15160192

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Jeffrey Junhao Xu ,  Kern Rim ,  Vladimir Machkaoutsan

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/267 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/785

Abstract: A device includes a substrate, a fin, and an isolation layer. The device also includes an epitaxial cladding layer on a sidewall of the fin. The epitaxial cladding layer has a substantially uniform thickness and has a continuous lattice structure at an interface with the sidewall. The epitaxial cladding layer is positioned above the isolation layer.

公开(公告)号：US20170110541A1

公开(公告)日：2017-04-20

申请号：US15198892

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/125 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.

公开(公告)号：US20170018620A1

公开(公告)日：2017-01-19

申请号：US14802479

申请日：2015-07-17

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/304 ,  H01L29/66 ,  G06F17/50 ,  H01L21/8238

CPC classification number: H01L29/4238 ,  G06F17/5077 ,  H01L21/3043 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

Abstract translation: 一种制造器件的方法包括执行栅极切割以切割栅极线以产生第一栅极区域和第二栅极区域。 该方法还包括沉积导电材料以形成导电跳线结构以连接第一栅区和第二栅区。

公开(公告)号：US09543248B2

公开(公告)日：2017-01-10

申请号：US14819159

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing Bao ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Niladri Narayan Mojumder ,  Choh Fei Yeap

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  B29C67/00 ,  G05B19/418 ,  B33Y50/02

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

Abstract translation: 集成电路器件包括包括铝的第一金属层。 集成电路器件包括具有互连结构的第二金属层。 互连结构包括一层包括铝的第一材料。 集成电路器件包括包括铝的互扩散层。 互扩散层靠近第一金属层并且靠近包括铝的第一材料层。 集成电路器件包括包含铝的自形成阻挡层。 自形成阻挡层靠近电介质层并且靠近包括铝的第一材料层。

公开(公告)号：US09502414B2

公开(公告)日：2016-11-22

申请号：US14633011

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。