公开(公告)号：US20160240673A1

公开(公告)日：2016-08-18

申请号：US15134935

申请日：2016-04-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.

公开(公告)号：US09368670B2

公开(公告)日：2016-06-14

申请号：US14692421

申请日：2015-04-21

Applicant: University of Oregon

Inventor： Shannon Boettcher ,  Andrew Ritenour ,  Jason Boucher ,  Ann Greenaway

IPC: H01L31/18 ,  H01L31/0304 ,  H01L31/0693 ,  H01L21/02 ,  C30B29/42 ,  C30B23/06

CPC classification number: H01L31/184 ,  C30B23/066 ,  C30B29/42 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02631 ,  H01L31/03042 ,  H01L31/0693 ,  H01L31/186 ,  Y02E10/50 ,  Y02E10/544 ,  Y02P70/521

Abstract: Disclosed herein are embodiments of methods for making GaAs thin films, such as photovoltaic GaAs thin films. The methods disclosed herein utilize sources, precursors, and reagents that do not produce (or require) toxic gas and that are readily available and relatively low in cost. In some embodiments, the methods are readily scalable for industrial applications and can provide GaAs thin films having properties that are at least comparable to or potentially superior to GaAs films obtained from conventional methods.

Abstract translation: 本文公开了用于制造GaAs薄膜的方法的实施例，例如光伏GaAs薄膜。 本文公开的方法利用不产生（或需要）有毒气体并且易于获得并且成本相对较低的来源，前体和试剂。 在一些实施例中，该方法对于工业应用来说易于扩展，并且可以提供具有至少与从常规方法获得的GaAs膜相当或潜在优越的性质的GaAs薄膜。

公开(公告)号：US20160163846A1

公开(公告)日：2016-06-09

申请号：US15009509

申请日：2016-01-28

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

公开(公告)号：US09337025B2

公开(公告)日：2016-05-10

申请号：US14129594

申请日：2012-07-13

Applicant: Yury Georgievich Shreter ,  Yury Toomasovich Rebane ,  Aleksey Vladimirovich Mironov

Inventor： Yury Georgievich Shreter ,  Yury Toomasovich Rebane ,  Aleksey Vladimirovich Mironov

IPC: H01L21/02 ,  H01L21/762 ,  H01L33/00

CPC classification number: H01L21/6835 ,  H01L21/02518 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/0257 ,  H01L21/02634 ,  H01L21/268 ,  H01L21/76254 ,  H01L33/0079 ,  H01L2221/68381

Abstract: The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same crystalline material as the epitaxial film. This new method of laser separation is based on using the selective doping of the substrate and epitaxial film with fine donor and acceptor impurities. In selective doping, concentration of free carries in the epitaxial film and substrate may essentially differ and this can lead to strong difference between the light absorption factors in the infrared region near the residual beams region where free carriers and phonon-plasmon interaction of the optical phonons with free carriers make an essential contribution to infrared absorption of the optical phonons. With the appropriate selection of the doping levels and frequency of infrared laser radiation it is possible to achieve that laser radiation is absorbed in general in the region of strong doping near the interface substrate-homoepitaxial film. When scanning the interface substrate-homoepitaxial film with the focused laser beam of sufficient power, thermal decomposition of the semiconductor crystal takes place with subsequent separation of the homoepitaxial film. The advantage of the proposed variations of the method for laser separation of epitaxial films in comparison with the known ones is in that it allows to separate homoepitaxial films from the substrates, i.e., homoepitaxial films having the same width of the forbidden gap as the initial semiconductor substrate has. The proposed variations of the method can be used for separation of the epitaxial films. Besides, the proposed method allows using the high-effective and inexpensive infrared gas silicon dioxide CO2 or silicon oxide CO lasers for separation of the epitaxial films.

Abstract translation: 本发明提出了激光分离方法的变化，其允许从与外延膜相同的结晶材料制成的基板上分离同质外延膜。 这种新的激光分离方法是基于使用具有精细施主和受主杂质的衬底和外延膜的选择性掺杂。 在选择性掺杂中，外延膜和衬底中的自由载流子的浓度可能基本上不同，并且这可能导致残余光束区域附近的红外区域中的光吸收因子之间的强烈差异，其中自由载流子和光子声子的声子等离子体相互作用 自由载体对光学声子的红外吸收作出重要贡献。 通过适当选择红外激光辐射的掺杂水平和频率，可以实现激光辐射通常在界面衬底 - 同质外延膜附近的强掺杂区域中被吸收。 当用具有足够功率的聚焦激光束扫描界面基底 - 同轴外延膜时，半导体晶体的热分解随后进行同质外延膜的分离。 与已知的相比，所提出的用于激光分离外延膜的方法的变化的优点在于它允许从基板分离同质外延膜，即具有与初始半导体相同宽度的禁止间隙的同质外延膜 底物有。 所提出的方法的变型可用于分离外延膜。 此外，所提出的方法允许使用高效且廉价的红外气体二氧化硅CO 2或氧化硅CO激光器来分离外延膜。

公开(公告)号：US20160099245A1

公开(公告)日：2016-04-07

申请号：US14504964

申请日：2014-10-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Balasubramanian PRANATHARTHIHARAN ,  Soon-Cheon SEO

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/0257 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

公开(公告)号：US09305766B2

公开(公告)日：2016-04-05

申请号：US13518259

申请日：2010-12-22

Applicant: Lars Samuelson ,  Knut Deppert ,  Jonas Ohlsson ,  Martin Magnusson

Inventor： Lars Samuelson ,  Knut Deppert ,  Jonas Ohlsson ,  Martin Magnusson

IPC: H01L21/326 ,  H01L21/00 ,  H01L21/38 ,  H01L21/302 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/06 ,  B03C7/00 ,  B82Y40/00

CPC classification number: H01L29/0669 ,  B03C7/00 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02 ,  H01L21/0257 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02628 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66136 ,  H01L29/66143 ,  H01L31/035227 ,  H01L31/068 ,  H01L31/072 ,  H01L31/18

Abstract: The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires (1) and applying an electrical field (E) over the population of nanowires (1), whereby an electrical dipole moment of the nanowires makes them align along the electrical field (E). Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate (2). The electrical field can be utilized in the deposition. Pn-junctions or any net charge introduced in the nanowires (1) may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.

Abstract translation: 本发明提供了一种用于对准纳米线的方法，其可用于制造包含纳米线的器件，所述纳米线在其布置在其上的衬底上独立地具有明确且受控的取向。 该方法包括以下步骤：在纳米线（1）群上提供纳米线（1）和施加电场（E），由此纳米线的电偶极矩使得它们沿着电场（E）排列。 优选地，在提供和对准的步骤期间，纳米线分散在流体中。 当对准时，可以将纳米线固定，优选沉积在基底（2）上。 电场可用于沉积。 在纳米线（1）中引入的Pn结或任何净电荷可能有助于对准和沉积过程。 该方法适用于连续加工，例如 在卷对卷方法中，几乎适用于任何基底材料，不限于适用于颗粒辅助生长的基底。

公开(公告)号：US09240317B2

公开(公告)日：2016-01-19

申请号：US14226883

申请日：2014-03-27

Applicant: UMM AL-QURA UNIVERSITY

Inventor： Elbadawy Elsharawy

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/20 ,  H01L29/26 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/0257 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/26 ,  H01L29/7787 ,  H01L2924/1077

Abstract: A low temperature GaN based super semiconductor comprising a GaN supercell having equal percentages of Cu and at least one material from the family of P, As, or Sb. The GaN supercell is doped in accordance with the formula Ga1-2xCuxAsxN, wherein x is from about 6.25% to about 25%. The supercell is deposited on GaN grown on silicon substrate.

Abstract translation: 一种低温GaN基超级半导体，包括具有相等百分比的Cu和至少一种来自P，As或Sb族的材料的GaN超晶胞。 根据式Ga1-2xCuxAsxN掺杂GaN超晶胞，其中x为约6.25％至约25％。 超晶胞沉积在生长在硅衬底上的GaN上。

公开(公告)号：US20160005660A1

公开(公告)日：2016-01-07

申请号：US14792024

申请日：2015-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsueh-Shih Fan ,  Sun-Jay Chang ,  Chia-Hsin Hu ,  Min-Chang Liang ,  Shien-Yang Wu ,  Wen-Hsing Hsieh ,  Ching-Fang Huang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/66136 ,  H01L29/861

Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.

Abstract translation: 公开了形成高效率的FinFET二极管的方法，其设计用于解决由于减小的有效面积而导致的传统FinFET二极管的劣化问题，以及制造方法。 FinFET二极管具有掺杂衬底，两个基本上平行的，等间隔的细长半导体鳍结构的两个间隔开的组，在两组之间和用于绝缘的翅片结构之间形成的电介质层，多个基本相等间隔并平行 垂直于翅片结构的两组横向延伸的细长门结构，以及分别在两组翅片结构上纵向形成的两组半导体条。 两组半导体条被掺杂以具有相反的导电类型，p型和n型。 FinFET二极管还具有形成在半导体条上的金属触点。 在一个实施例中，半导体条可以通过外延生长和原位掺杂与翅片结构整体形成。

公开(公告)号：US20150380528A1

公开(公告)日：2015-12-31

申请号：US14846020

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jing Lee ,  Chi-Wen Liu ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L21/308 ,  H01L21/3105

CPC classification number: H01L29/161 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66712 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7802 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract translation: 一种器件包括衬底和衬底的一部分上的绝缘区域。 第一半导体区域在绝缘区域之间并且具有第一导带。 第二半导体区域在第一半导体区域的上方并且邻接，其中第二半导体区域包括高于绝缘区域的顶表面的上部，以形成半导体鳍片。 第二半导体区域还包括在宽部分上的宽部分和窄部分，其中窄部分比宽部分窄。 半导体鳍具有拉伸应变，并且具有比第一导带低的第二导带。 第三半导体区域在半导体鳍片的上表面和侧壁的上方邻接，其中第三半导体区域具有比第二导带高的第三导带。

公开(公告)号：US20150348851A1

公开(公告)日：2015-12-03

申请号：US14822959

申请日：2015-08-11

Applicant: STMicroelectronics, Inc.

Inventor： Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract translation: 将半导体材料图案化以限定与底层基板绝缘的细长翅片。 多晶硅半导体材料沉积在细长翅片之上并在细长翅片之间，并且被图案化以限定延伸到在晶体管沟槽处垂直交叉在细长翅片上的细长门。 侧壁间隔件形成在细长门的侧壁上。 位于细长门之间的细长翅片的部分与下面的绝缘体一起被去除以暴露下面的基底。 然后在细长门之间的位置从下面的衬底外延生长一个或多个半导体材料层。 一个或多个半导体材料层可以包括未掺杂的外延层和上覆的掺杂外延层。 外延材料限定晶体管的源极或漏极。