公开(公告)号：US09293378B2

公开(公告)日：2016-03-22

申请号：US14792024

申请日：2015-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsueh-Shih Fan ,  Sun-Jay Chang ,  Chia-Hsin Hu ,  Min-Chang Liang ,  Shien-Yang Wu ,  Wen-Hsing Hsieh ,  Ching-Fang Huang

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/66136 ,  H01L29/861

Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.

Abstract translation: 公开了形成高效率的FinFET二极管的方法，其设计用于解决由于减小的有效面积而导致的传统FinFET二极管的劣化问题，以及制造方法。 FinFET二极管具有掺杂衬底，两个基本上平行的，等间隔的细长半导体鳍结构的两个间隔开的组，在两组之间和用于绝缘的鳍结构之间形成的介电层，多个基本相等间隔并平行 垂直于翅片结构的两组横向延伸的细长门结构，以及分别在两组翅片结构上纵向形成的两组半导体条。 两组半导体条被掺杂以具有相反的导电类型，p型和n型。 FinFET二极管还具有形成在半导体条上的金属触点。 在一个实施例中，半导体条可以通过外延生长和原位掺杂与翅片结构整体形成。

公开(公告)号：US08946038B2

公开(公告)日：2015-02-03

申请号：US14088538

申请日：2013-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Sun-Jay Chang ,  Jaw-Juinn Horng ,  Chung-Hui Chen

IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L27/08

CPC classification number: H01L27/0623 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/0814 ,  H01L29/861

Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.

Abstract translation: 在鳍状场效应晶体管（FinFET）器件中形成一个或多个二极管的方法包括形成具有鳍状图案的硬掩模层，所述鳍状图案包括隔离的鳍片区域，鳍片阵列区域和FinFET区域。 该方法还包括使用鳍状图案将多个鳍片刻蚀成半导体衬底，并在半导体衬底上沉积介电材料以填充多个鳍片之间的空间。 该方法还包括平面化半导体衬底以暴露硬掩模层。 该方法还包括将p型掺杂剂注入鳍阵列区域和FinFET区域的部分，以及将n型掺杂剂注入到隔离鳍片区域中，围绕p阱的鳍阵列区域的一部分和部分 的FinFET区域。 该方法还包括退火半导体衬底。

公开(公告)号：US09514989B2

公开(公告)日：2016-12-06

申请号：US14719586

申请日：2015-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Min-Chang Liang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a semiconductor fin, which forms a ring, forming a plurality of gate stacks on sidewalls and a top surface of each of sides of the ring, epitaxially growing a plurality of epitaxy regions between the plurality of gate stacks, and forming a plurality of metal contact plugs. Each of the plurality of metal contact plugs is over, and is electrically coupling to, one of the plurality of epitaxy regions.

Abstract translation: 一种方法包括形成半导体翅片，其形成环，在环的每个侧面的侧壁和顶表面上形成多个栅极叠层，在多个栅极堆叠之间外延生长多个外延区域，并形成 多个金属接触塞。 多个金属接触插塞中的每一个在多个外延区域中的一个上结束并且电耦合。

公开(公告)号：US09076869B1

公开(公告)日：2015-07-07

申请号：US14150588

申请日：2014-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Sun-Jay Chang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.

Abstract translation: 引入了鳍状场效应晶体管（FinFET）和制造方法。 在一个实施例中，沟槽形成在衬底中，其中相邻沟槽之间的区域限定鳍。 在沟槽中形成电介质材料。 衬底的一部分被掺杂，并且形成高掺杂剂浓度的区域和低掺杂剂浓度的区域。 形成栅极堆叠，去除部分散热片，并在高/低掺杂浓度的区域中外延生长源极/漏极区域。 形成触点以提供与源极/栅极/漏极区域的电接触。

公开(公告)号：US09780003B2

公开(公告)日：2017-10-03

申请号：US15237226

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Hsin Hu ,  Min-chang Liang ,  Sun-Jay Chang ,  Shien-Yang Wu

IPC: H01L21/8249 ,  H01L29/417 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/0692 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66795 ,  H01L29/732 ,  H01L29/735

Abstract: A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.

公开(公告)号：US09755075B2

公开(公告)日：2017-09-05

申请号：US15076205

申请日：2016-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsueh-Shih Fan ,  Ching-Fang Huang ,  Chia-Hsin Hu ,  Min-Chang Liang ,  Sun-Jay Chang ,  Shien-Yang Wu ,  Wen-Hsing Hsieh

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/861 ,  H01L21/02 ,  H01L21/265 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/66136 ,  H01L29/861

Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.

公开(公告)号：US09679992B2

公开(公告)日：2017-06-13

申请号：US15042300

申请日：2016-02-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Sun-Jay Chang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET) and a method of forming the same are introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.

公开(公告)号：US20150194524A1

公开(公告)日：2015-07-09

申请号：US14150588

申请日：2014-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Hsin Hu ,  Sun-Jay Chang

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/1041 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.

Abstract translation: 引入了鳍状场效应晶体管（FinFET）和制造方法。 在一个实施例中，沟槽形成在衬底中，其中相邻沟槽之间的区域限定鳍。 在沟槽中形成电介质材料。 衬底的一部分被掺杂，并且形成高掺杂剂浓度的区域和低掺杂剂浓度的区域。 形成栅极堆叠，去除部分散热片，并在高/低掺杂浓度的区域中外延生长源极/漏极区域。 形成触点以提供与源极/栅极/漏极区域的电接触。

公开(公告)号：US09053947B2

公开(公告)日：2015-06-09

申请号：US14166510

申请日：2014-01-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Min-Chang Liang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not covered by the gate stack to form a recess. The method further includes performing an epitaxy to grow an epitaxy semiconductor region from the recess, forming a first contact plug overlying and electrically coupled to the epitaxy semiconductor region, and forming a second contact plug, wherein the second contact plug is overlying and electrically coupled to the gate stack.

Abstract translation: 一种方法包括在半导体鳍片上形成栅极堆叠，其中半导体鳍片形成环，并且蚀刻未被栅极叠层覆盖的半导体鳍片的一部分以形成凹陷。 所述方法还包括执行外延以从所述凹部生长外延半导体区域，形成覆盖并电耦合到所述外延半导体区域的第一接触插塞，以及形成第二接触插塞，其中所述第二接触插塞被覆盖并电耦合到 门堆叠。

公开(公告)号：US20140141586A1

公开(公告)日：2014-05-22

申请号：US14166510

申请日：2014-01-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Min-Chang Liang

IPC: H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric. The device further includes a plurality of semiconductor regions, each disposed between and contacting two neighboring ones of the plurality of semiconductor fins. The device further includes a plurality of contact plugs, each overlying and electrically coupled to one of the plurality of semiconductor regions. An electrical connection electrically interconnects the plurality of semiconductor regions and the gate electrodes of the plurality of gate stacks.

Abstract translation: 一种器件包括半导体衬底，延伸到半导体衬底中的隔离区域，高于隔离区域顶表面的多个半导体鳍片，以及多个栅极叠层。 每个栅极堆叠包括顶表面上的栅极电介质和多个半导体鳍之一的侧壁以及栅极电介质上的栅电极。 该器件还包括多个半导体区域，每个半导体区域设置在多个半导体鳍片中并与两个相邻的半导体鳍片接触。 该装置还包括多个接触插塞，每个接触插塞各自覆盖并电耦合到多个半导体区域中的一个。 电连接将多个栅极堆叠中的多个半导体区域和栅电极电连接。