公开(公告)号：US09281183B2

公开(公告)日：2016-03-08

申请号：US14597989

申请日：2015-01-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L21/00 ,  H01L29/00 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  C30B25/02 ,  H01L29/20

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Abstract translation: 一种制造III族氮化物半导体器件的方法，包括在氧化物生长和III族氮化物半导体的生长之间不暴露于空气中，依次生长III族氮化物半导体和氧化物以形成氧化物/ III族氮化物界面 。

公开(公告)号：US10312361B2

公开(公告)日：2019-06-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20170125574A1

公开(公告)日：2017-05-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20160163846A1

公开(公告)日：2016-06-09

申请号：US15009509

申请日：2016-01-28

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

公开(公告)号：US20150200286A1

公开(公告)日：2015-07-16

申请号：US14597989

申请日：2015-01-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Abstract translation: 一种制造III族氮化物半导体器件的方法，包括在氧化物生长和III族氮化物半导体的生长之间不暴露于空气中，依次生长III族氮化物半导体和氧化物以形成氧化物/ III族氮化物界面 。