Abstract:
Exemplary methods of semiconductor processing may include treating a surface of a substrate with a hydrogen-containing precursor. The substrate may be disposed within a processing region of a semiconductor processing chamber. The methods may include contacting the substrate with a tungsten-containing precursor. The methods may include forming an initiation layer comprising tungsten on the substrate. The methods may include treating the initiation layer with a hydrogen-containing precursor. The methods may include forming a plasma of the tungsten-containing precursor and a carbon-containing precursor. Hydrogen in the plasma may be limited to hydrogen included in the carbon-containing precursor. The methods may include forming a tungsten-containing hardmask layer on the initiation layer.
Abstract:
A vapor phase epitaxial growth device comprises a reactor vessel and a wafer holder arranged within the reactor vessel. The wafer holder includes a wafer holding surface configured to hold a wafer with a wafer surface oriented substantially vertically downward. The device comprises a first material gas supply pipe configured to supply a first material gas and arranged below the wafer holding surface. The device comprises a second material gas supply pipe configured to supply a second material gas and arranged below the wafer holding surface. The device comprises a gas exhaust pipe configured to exhaust gases and arranged below the wafer holding surface. A distance between the gas exhaust pipe and an axis line passing through a center of the wafer holding surface is greater than distances between the axis line and each of the first material gas supply pipe and the second material gas supply pipe.
Abstract:
A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming the line mask comprises forming parallel material lines extending in a longitudinal direction, wherein forming the mandrel mask comprises forming a mandrel mask having sidewalls including at least a first sidewall extending transverse to a plurality of the material lines; (ii) forming on the sidewalls of the mandrel mask a sidewall spacer including a first sidewall spacer portion extending along the first sidewall; (iii) partially removing the sidewall spacer such that a remainder of the sidewall spacer comprises at least a part of the first sidewall spacer portion; and (iv) subsequent to removing the mandrel mask, transferring into the target layer a pattern defined by the line mask and the remainder of the sidewall spacer.
Abstract:
A graphene compound made from the method of preparing graphene flakes or chemical vapor deposition grown graphene films on a SiO2/Si substrate; exposing the graphene flakes or the chemical vapor deposition grown graphene film to hydrogen plasma; performing hydrogenation of the graphene; wherein the hydrogenated graphene has a majority carrier type; creating a bandgap from the hydrogenation of the graphene; applying an electric field to the hydrogenated graphene; and tuning the bandgap.
Abstract:
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.
Abstract:
In one embodiment, a method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and an aromatic solvent, introducing one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, reacting the precursors in the reaction mixture, without the addition of an acid compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals, and wherein an amide compound is formed in situ in the reaction mixture prior to isolating the coated semiconductor nanocrystals. In another embodiment, method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and a solvent, introducing an amide compound, one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, and reacting the precursors in the reaction mixture in the presence of the amide compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals. Semiconductor nanocrystals including coatings grown in accordance with the above methods are also disclosed.
Abstract:
A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
Abstract:
A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.
Abstract:
A computer program storage product includes instructions for forming a fin field-effect-transistor. The instructions are configured to perform a method. The method includes implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor.
Abstract:
A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.