公开(公告)号：US09997417B2

公开(公告)日：2018-06-12

申请号：US15355483

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Tsun Liu

IPC: H01L21/311 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/441 ,  H01L21/465 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/26 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L21/823864 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/441 ,  H01L21/465 ,  H01L21/823814 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/26 ,  H01L29/4232 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

公开(公告)号：US09991339B2

公开(公告)日：2018-06-05

申请号：US15364578

申请日：2016-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US09991205B2

公开(公告)日：2018-06-05

申请号：US15394003

申请日：2016-12-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L23/535 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L23/535 ,  H01L21/76224 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53257 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating material over a substrate, and forming a first conductive contact in the first insulating material. The first conductive contact has a protruding uppermost surface, with a first height along a central portion of the first conductive contact, and a second height along a vertical vector projection of a sidewall of the first conductive contact. The first height is larger than the second height. A second insulating material is deposited over the first insulating material, and a second conductive contact is formed in the second insulating material. The second conductive contact is disposed over and at least partially within the first conductive contact. A distance between a bottommost surface of the second conductive contact and the protruding uppermost surface of the first conductive contact is less than about 1.0 nm.

公开(公告)号：US20180151732A1

公开(公告)日：2018-05-31

申请号：US15575008

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  ANAND S. MURTHY ,  TAHIR GHANI ,  GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  SEAN T. MA ,  CORY E. WEBER

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are disclosed for resistance reduction in p-MOS transistors having epitaxially grown boron-doped silicon germanium (SiGe:B) S/D regions. The techniques can include growing one or more interface layers between a silicon (Si) channel region of the transistor and the SiGe:B replacement S/D regions. The one or more interface layers may include: a single layer of boron-doped Si (Si:B); a single layer of SiGe:B, where the Ge content in the interface layer is less than that in the resulting SiGe:B S/D regions; a graded layer of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage; or multiple stepped layers of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage at each step. Inclusion of the interface layer(s) reduces resistance for on-state current flow.

公开(公告)号：US20180151730A1

公开(公告)日：2018-05-31

申请号：US15418023

申请日：2017-01-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

公开(公告)号：US09985117B2

公开(公告)日：2018-05-29

申请号：US15588969

申请日：2017-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L21/3065

CPC classification number: H01L21/02645 ,  H01L21/02236 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76202 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

公开(公告)号：US09985036B2

公开(公告)日：2018-05-29

申请号：US15291265

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC: H01L29/78 ,  H01L27/11 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/161 ,  H01L27/088 ,  H01L29/45 ,  H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

公开(公告)号：US20180145174A1

公开(公告)日：2018-05-24

申请号：US15860292

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  B82Y10/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US20180122916A1

公开(公告)日：2018-05-03

申请号：US15682873

申请日：2017-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  The Regents of the University of California

Inventor： Zi-Wei FANG ,  Hong-Fa LUAN ,  Wilman TSAI ,  Kasra SARDASHTI ,  Maximillian CLEMONS ,  Scott UEDA ,  Mahmut KAVRIK ,  Iljo KWAK ,  Andrew KUMMEL ,  Hsiang-Pi CHANG

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/94 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/66189 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785 ,  H01L29/94

Abstract: The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.

公开(公告)号：US20180122743A1

公开(公告)日：2018-05-03

申请号：US15851640

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Yao LAI ,  Sai-Hooi YEONG ,  Ying-Yan CHEN

IPC: H01L23/535 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.