知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

130 records (took 0.028 seconds)

    CHIPLET ARCHITECTURE FOR INFERENCE, FINE-TUNING TRAINING, AND TRANSFER LEARNING
    1.
    发明申请
    CHIPLET ARCHITECTURE FOR INFERENCE, FINE-TUNING TRAINING, AND TRANSFER LEARNING 有权

    公开(公告)号：US20250005371A1

    公开(公告)日：2025-01-02

    申请号：US18217522

    申请日：2023-06-30

    Applicant: International Business Machines Corporation

    Inventor： Arvind Kumar ,  Mudhakar Srivatsa ,  Raghu Kiran Ganti ,  Joshua M. Rubin

    IPC: G06N3/096 ,  G06N3/04

    Abstract: A method for training and fine-tuning an artificial intelligence model is disclosed. In one embodiment, such a method distributes, across multiple chiplets of a package, functionality associated with a deep neural network. The method implements, within a first set of chiplets, frozen layers of the deep neural network. By contrast, the method implements, within a second set of chiplets, trainable layers of the deep neural network. The number of chiplets in the second set may be smaller than the number of chiplets in the first set and may consist of a single chiplet in some embodiments. In certain embodiments, the second set of chiplets has one or more of additional memory capacity and additional processing capacity compared to the first set of chiplets in order to train and fine tune the trainable layers. A corresponding apparatus is also disclosed.

    Micro-fluidic channels having various critical dimensions
    5.
    发明授权
    Micro-fluidic channels having various critical dimensions 有权

    公开(公告)号：US11081424B2

    公开(公告)日：2021-08-03

    申请号：US16444383

    申请日：2019-06-18

    Applicant: International Business Machines Corporation

    Inventor： Ravi K. Bonam ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Iqbal Rashid Saraf ,  Fee Li Lie

    IPC: H01L23/473 ,  H01L21/768 ,  F28F3/12

    Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.

    MULTI-CHIP PACKAGE STRUCTURES FORMED BY JOINING CHIPS TO PRE-POSITIONED CHIP INTERCONNECT BRIDGE DEVICES
    6.
    发明申请
    MULTI-CHIP PACKAGE STRUCTURES FORMED BY JOINING CHIPS TO PRE-POSITIONED CHIP INTERCONNECT BRIDGE DEVICES 有权

    公开(公告)号：US20210159211A1

    公开(公告)日：2021-05-27

    申请号：US16697682

    申请日：2019-11-27

    Applicant: International Business Machines Corporation

    Inventor： Joshua M. Rubin ,  Steven Lorenz Wright ,  Lawrence A. Clevenger

    IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56

    Abstract: Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.

    MULTIPLE CHIP BRIDGE CONNECTOR
    7.
    发明申请
    MULTIPLE CHIP BRIDGE CONNECTOR 有权

    公开(公告)号：US20210020529A1

    公开(公告)日：2021-01-21

    申请号：US16517568

    申请日：2019-07-20

    Applicant: International Business Machines Corporation

    Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Courmoyer

    IPC: H01L23/13 ,  H01L23/538 ,  H01L23/532 ,  H01L27/24

    Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

    High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations
    9.
    发明授权
    High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations 有权

    公开(公告)号：US10714420B1

    公开(公告)日：2020-07-14

    申请号：US16237958

    申请日：2019-01-02

    Applicant: International Business Machines Corporation

    Inventor： Joshua M. Rubin ,  Joel A. Silberman ,  Robert Groves

    IPC: H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/66

    Abstract: Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor. The truncated via contacts allow for higher density via contact connections to the capacitor electrodes in regions which have a dense array of wiring of a single polarity, where interlevel via contacts cannot be utilized to provide contacts to the capacitor electrodes.

    INTERLAYER VIA CONTACTS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
    10.
    发明申请
    INTERLAYER VIA CONTACTS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES 审中-公开

    公开(公告)号：US20200126987A1

    公开(公告)日：2020-04-23

    申请号：US16166996

    申请日：2018-10-22

    Applicant: International Business Machines Corporation

    Inventor： Joshua M. Rubin ,  Nicolas Loubet ,  Terence B. Hook

    IPC: H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8238

    Abstract: Devices and methods are provided for fabricating metallic interlayer via contacts within source/drain regions of field-effect transistor devices of a monolithic three-dimensional semiconductor integrated circuit device. For example, a semiconductor integrated circuit device includes a first device layer and a second device layer disposed on the first device layer. The first device layer includes a metallic interconnect structure formed in an insulating layer. The second device layer includes first and second field-effect transistor devices having respective first and second gate structures. A metallic interlayer via contact is disposed between the first and second gate structures in contact with the metallic interconnect structure of the first device layer, wherein a width of the metallic interlayer via contact is defined by a spacing between adjacent sidewalls of the first and second gate structures. Epitaxial source/drain layers for the first and second field-effect transistor devices are embedded within the metallic interlayer via contact.

Patent Agency Ranking