公开(公告)号：US20230268275A1

公开(公告)日：2023-08-24

申请号：US17651883

申请日：2022-02-21

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  James J. Kelly ,  Eric Perfecto ,  SPYRIDON SKORDAS ,  Dale Curtis McHerron

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/5329 ,  H01L24/05 ,  H01L21/02118 ,  H01L2924/01029 ,  H01L2224/024

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

公开(公告)号：US11791270B2

公开(公告)日：2023-10-17

申请号：US17315859

申请日：2021-05-10

Applicant: International Business Machines Corporation

Inventor： Kamal K Sikka ,  Maryse Cournoyer ,  Pascale Gagnon ,  Charles C. Bureau ,  Catherine Dufort ,  Dale Curtis McHerron ,  Vijayeshwar Das Khanna ,  Marc A. Bergendahl ,  Dishit Paresh Parekh ,  Ravi K. Bonam ,  Hiroyuki Mori ,  Yang Liu ,  Paul S. Andry ,  Isabel De Sousa

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/16257 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/1616 ,  H01L2924/1632 ,  H01L2924/3512

Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

公开(公告)号：US20210020529A1

公开(公告)日：2021-01-21

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Courmoyer

IPC: H01L23/13 ,  H01L23/538 ,  H01L23/532 ,  H01L27/24

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

公开(公告)号：US20240332239A1

公开(公告)日：2024-10-03

申请号：US18191950

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander Polomoff ,  Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Eric Perfecto ,  Katsuyuki Sakuma ,  SPYRIDON SKORDAS

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/80357 ,  H01L2224/95

Abstract: A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.

公开(公告)号：US20220359401A1

公开(公告)日：2022-11-10

申请号：US17315859

申请日：2021-05-10

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Maryse Cournoyer ,  Pascale Gagnon ,  Charles C. Bureau ,  Catherine Dufort ,  Dale Curtis McHerron ,  Vijayeshwar Das Khanna ,  Marc A. Bergendahl ,  Dishit Paresh Parekh ,  RAVI K. BONAM ,  HIROYUKI MORI ,  Yang Liu ,  Paul S. Andry ,  Isabel De Sousa

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/13 ,  H01L21/48

Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

公开(公告)号：US11355379B1

公开(公告)日：2022-06-07

申请号：US17103793

申请日：2020-11-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Spyridon Skordas

IPC: H01L21/683 ,  H01L23/48 ,  H01L21/768

Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.

公开(公告)号：US20220165601A1

公开(公告)日：2022-05-26

申请号：US17103793

申请日：2020-11-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Spyridon Skordas

IPC: H01L21/683 ,  H01L23/48 ,  H01L21/768

Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.

公开(公告)号：US10991635B2

公开(公告)日：2021-04-27

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Cournoyer

IPC: H01L23/538 ,  H01L23/13 ,  H01L27/24 ,  H01L23/532

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.