Active control for two-phase cooling

    公开(公告)号:US11464137B2

    公开(公告)日:2022-10-04

    申请号:US15981067

    申请日:2018-05-16

    IPC分类号: H05K7/20 F28D15/02 F28D15/06

    摘要: A cooling system includes a device to be cooled and a cooling device integrated with the device to be cooled. A cooling volume has cavities and active coolant flow controls configured to adjust coolant flow through the cavities. A reservoir is in fluid communication with the cavities and has a liquid outlet and an inlet for a gas or gas-liquid mixture. A two-phase coolant is in the reservoir and cavities. The two-phase coolant has a phase transition temperature between an ambient temperature and an expected device temperature. A capacitance sensor is configured to determine a coolant capacitance in the cavities. A control module is configured to determine a vapor quality and void fraction of the coolant based on the measured capacitance and to increase coolant flow if the determined vapor quality and void fraction indicate a dry-out condition. A secondary cooling line removes heat from the cooling device.

    Half-precision floating-point arrays at low overhead

    公开(公告)号:US11281745B2

    公开(公告)日:2022-03-22

    申请号:US16542447

    申请日:2019-08-16

    IPC分类号: G06F17/16 G06F7/544

    摘要: Methods and systems of matrix multiplication are described. In an example, a processor can multiply a first entry of a first vector of a first data array with a second vector of a second data array to generate a third vector of a third data array. The processor can store the third vector of the third data array in the second register file. The processor can multiply a second entry of the first vector with the second vector to generate a fourth vector of the third data array. The processor can store the fourth vector of the third data array in the second register file. The processor can combine vectors of the third data array that are stored in the second register file to produce the third data array.

    COALESCING GLOBAL COMPLETION TABLE ENTRIES IN AN OUT-OF-ORDER PROCESSOR

    公开(公告)号:US20200150969A1

    公开(公告)日:2020-05-14

    申请号:US16738360

    申请日:2020-01-09

    IPC分类号: G06F9/38

    摘要: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

    Active control for two-phase cooling

    公开(公告)号:US09986662B2

    公开(公告)日:2018-05-29

    申请号:US15614936

    申请日:2017-06-06

    IPC分类号: H05K7/20 F28D15/02 F28D15/06

    摘要: A cooling system includes a device to be cooled and a cooling device integrated with the device to be cooled. A cooling volume has cavities and active coolant flow controls configured to adjust coolant flow through the cavities. A reservoir is in fluid communication with the cavities and has a liquid outlet and an inlet for a gas or gas-liquid mixture. A two-phase coolant is in the reservoir and cavities. The two-phase coolant has a phase transition temperature between an ambient temperature and an expected device temperature. A capacitance sensor is configured to determine a coolant capacitance in the cavities. A control module is configured to determine a vapor quality and void fraction of the coolant based on the measured capacitance and to increase coolant flow if the determined vapor quality and void fraction indicate a dry-out condition. A secondary cooling line removes heat from the cooling device.

    Instruction selection mechanism with class-dependent age-array

    公开(公告)号:US11106469B2

    公开(公告)日:2021-08-31

    申请号:US16540489

    申请日:2019-08-14

    发明人: Joel A. Silberman

    IPC分类号: G06F9/38

    摘要: Methods and systems for implementing an instruction selection mechanism with class-dependent age-array are described. In an example, a system can include a processor that may sequence instructions. The system can further include a memory operatively coupled to the processor. The system can further include an array allocated on the memory. The array can be operable to store instruction age designations associated with a plurality of instructions sequenced by the processor. The array can be further operable to store the instruction age designations based on instruction classes. The processor can be operable to fetch an instruction from the memory. The processor can be operable to dispatch the instruction to a queue. The processor can be operable to store the instruction age designations associated with the instruction, in the array, based on an instruction class of the instruction.

    Scalable dependency matrix with a single summary bit in an out-of-order processor

    公开(公告)号:US10929140B2

    公开(公告)日:2021-02-23

    申请号:US15826734

    申请日:2017-11-30

    IPC分类号: G06F9/30 G06F9/38

    摘要: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions in a group of instructions in the issue queue that were added to the issue queue prior to the instruction and that are not included in the threshold number of instructions that are tracked individually. A dependency between the instruction and the one or more other instructions in the group of instructions is tracked using a single summary bit that is set to indicate that a dependency exists between the instruction and the group of instructions. Instructions are issued from the issue queue based at least in part on the tracking.

    Issue queue with dynamic shifting between ports

    公开(公告)号:US10884753B2

    公开(公告)日:2021-01-05

    申请号:US15826745

    申请日:2017-11-30

    IPC分类号: G06F9/38 G06F9/30

    摘要: Aspects include monitoring a number of instructions of a first type dispatched to a first shared port of an issue queue of a processor and determining whether the number of instructions of the first type dispatched to the first shared port exceeds a port selection threshold. An instruction of a third type is dispatched to a second shared port of the issue queue associated with a plurality of instructions of a second type based on determining that the number of instructions of the first type dispatched to the first shared port exceeds the port selection threshold. The instruction of the third type is dispatched to the first shared port of the issue queue associated with a plurality of instructions of the first type based on determining that the number of instructions of the first type dispatched to the first shared port does not exceed the port selection threshold.

    Scalable dependency matrix with multiple summary bits in an out-of-order processor

    公开(公告)号:US10564976B2

    公开(公告)日:2020-02-18

    申请号:US15826746

    申请日:2017-11-30

    IPC分类号: G06F9/30 G06F9/38

    摘要: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked as a plurality of groups by indicating that a dependency exists between the instruction and one of the groups based on identifying a dependency between the instruction and at least one instruction in the group. Instructions are issued from the issue queue based at least in part on the tracking.

    COALESCING GLOBAL COMPLETION TABLE ENTRIES IN AN OUT-OF-ORDER PROCESSOR

    公开(公告)号:US20190163490A1

    公开(公告)日:2019-05-30

    申请号:US15826752

    申请日:2017-11-30

    IPC分类号: G06F9/38

    摘要: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.