公开(公告)号：US20100032712A1

公开(公告)日：2010-02-11

申请号：US12186231

申请日：2008-08-05

申请人： Florin UDREA ,  Vasantha PATHIRANA ,  Tanya TRAJKOVIC ,  Nishad UDUGAMPOLA

发明人： Florin UDREA ,  Vasantha PATHIRANA ,  Tanya TRAJKOVIC ,  Nishad UDUGAMPOLA

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0839 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7394 ,  H01L29/7824

摘要： A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

摘要翻译： 功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。 装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。 顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。 在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。 器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。 该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

公开(公告)号：US12074198B2

公开(公告)日：2024-08-27

申请号：US17453300

申请日：2021-11-02

申请人： Analog Power Conversion LLC

发明人： Amaury Gendron-Hansen ,  Dumitru Gheorge Sdrulla ,  Leslie Louis Szepesi

IPC分类号： H01L29/06 ,  G06F30/39 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G06F119/08 ,  H01L29/16

CPC分类号： H01L29/0696 ,  G06F30/39 ,  H01L29/0856 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7802 ,  G06F2119/08 ,  H01L29/1608

摘要： A tub of a semiconductor device includes a cool zone with a first projected operating temperature and a hot zone with a second projected operating temperature greater than the first projected operating temperature. A design parameter has a first value in the cool zone and a second value different from the first value in the hot zone. The difference configures the tub to dissipate less heat in the hot zone during operation of the semiconductor device than would be dissipated if the first and second values were equal. The design parameter may be, for example, a tub width, a source structure width, a JFET region width, a channel length, a channel width, a length of a gate, a displacement of a center of the gate relative to a center of a JFET region, a dopant concentration, or a combination thereof.

公开(公告)号：US20240170566A1

公开(公告)日：2024-05-23

申请号：US18283169

申请日：2022-02-18

申请人： HITACHI ENERGY LTD

发明人： Andrei MIHAILA ,  Munaf RAHIMO ,  Lars KNOLL ,  Marco BELLINI

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/7802 ,  H01L29/0692 ,  H01L29/0856 ,  H01L29/1608 ,  H01L29/66712 ,  H01L29/7395

摘要： A power semiconductor device (1) is provided, comprising



a drift layer (2) of a first conductivity type,
at least two well regions (3) of a second conductivity type being different from the first conductivity type, and
at least one intermediate region (4), wherein
the at least two well regions (3) and the at least one intermediate region (4) are provided within the drift layer (2) at a first side,
the at least one intermediate region (4) is provided between the at least two well regions (3), and
the at least one intermediate region (4) comprises at least one first doped region (5) of the first conductivity type and at least one second doped region (6) of the second conductivity type.

公开(公告)号：US20230411519A1

公开(公告)日：2023-12-21

申请号：US18462002

申请日：2023-09-06

申请人： Key Foundry Co., Ltd.

发明人： Jin Seong CHUNG ,  Tae Hoon LEE

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0856 ,  H01L29/7816 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/0886

摘要： A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

公开(公告)号：US11695040B2

公开(公告)日：2023-07-04

申请号：US17210635

申请日：2021-03-24

申请人： Government of the United States, as represented by the Secretary of the Air Force

发明人： Kelson D Chabak ,  Andrew J Green ,  Gregg H Jessen

IPC分类号： H01L29/08 ,  H01L29/417

CPC分类号： H01L29/0873 ,  H01L29/0856 ,  H01L29/41775

摘要： Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Ecrit semiconductors are presented. A dielectric layer is deposited on a high Ecrit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Ecrit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Ecrit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

公开(公告)号：US20190067424A1

公开(公告)日：2019-02-28

申请号：US16048488

申请日：2018-07-30

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： CHIAKI KUDOU

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/28052 ,  H01L21/31056 ,  H01L21/32135 ,  H01L21/76828 ,  H01L23/5329 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802

摘要： Provided is a silicon carbide semiconductor device that is further reduced in resistance. Silicon carbide semiconductor device includes silicon carbide semiconductor layer disposed on a first main surface of substrate, electrode layer containing polysilicon disposed on the silicon carbide semiconductor layer with first insulating layer interposed between the electrode layer and the silicon carbide semiconductor layer, second insulating layer that covers the silicon carbide semiconductor layer and the electrode layer, first silicide electrode that is located in first opening part formed in the first insulating layer and the second insulating layer and forms ohmic contact with a part of the silicon carbide semiconductor layer, and second silicide electrode that is located in second opening part formed in the second insulating layer and is in contact with a part of the electrode layer.

公开(公告)号：US20180138906A9

公开(公告)日：2018-05-17

申请号：US14585201

申请日：2014-12-30

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H03K17/687 ,  H01H49/00

CPC分类号： H01H49/00 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/122 ,  H03K17/164 ,  H03K17/687 ,  Y10T29/49105 ,  Y10T307/747 ,  Y10T307/76 ,  H01L2924/00

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

公开(公告)号：US20180097063A1

公开(公告)日：2018-04-05

申请号：US15719607

申请日：2017-09-29

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hideaki MATSUYAMA ,  Shinya TAKASHIMA ,  Katsunori UENO ,  Takuro INAMOTO ,  Masaharu EDO

IPC分类号： H01L29/10 ,  H01L29/20 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L29/1095 ,  H01L21/0254 ,  H01L21/26546 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66734 ,  H01L29/7813

摘要： In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.

公开(公告)号：US20180097061A1

公开(公告)日：2018-04-05

申请号：US15560662

申请日：2016-03-10

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Tomohiro MIMURA ,  Takashi KANEMURA ,  Masahiro SUGIMOTO ,  Narumasa SOEJIMA

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/16

CPC分类号： H01L29/105 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7813

摘要： A semiconductor device includes: a drain region; a drift layer made of a first conductivity type semiconductor with lower impurity concentration than the drain region; a base region made of a second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity type semiconductor with higher concentration; a trench structure having a first gate insulation film and a first gate electrode arranged at an opening side of the trench and to be deeper than the base region, and a bottom part insulation film; a source electrode electrically connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The drain is arranged to be deeper than the base region. The first gate insulation film is made of higher dielectric insulation material than the bottom part insulation film.

公开(公告)号：US09806167B2

公开(公告)日：2017-10-31

申请号：US14908941

申请日：2014-06-19

申请人： Sumitomo Electric Industries, Ltd.

发明人： Taku Horii ,  Takeyoshi Masuda ,  Ryosuke Kubota

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L21/04 ,  H01L29/10

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

摘要： The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.