公开(公告)号：US12136652B2

公开(公告)日：2024-11-05

申请号：US17595457

申请日：2020-05-22

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Taku Horii

IPC: H01L29/16 ,  H01L21/28 ,  H01L23/00 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulator provided on a surface of the semiconductor substrate, a bonding film, including silicon or aluminum, provided on the gate insulator, and a gate pad layer provided above the bonding film, wherein the gate pad layer includes titanium in at least a region in contact with the bonding film.

公开(公告)号：US09768125B2

公开(公告)日：2017-09-19

申请号：US14712354

申请日：2015-05-14

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Toru Hiyoshi ,  Taku Horii

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L23/58 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0485 ,  H01L21/32051 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3192 ,  H01L23/585 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7811 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2224/03

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The metal layer extends to cover at least a portion of a sidewall of the step portion. The method of manufacturing the semiconductor device further includes dividing the semiconductor layer into element regions on an outside of the step portion when viewed from the element region.

公开(公告)号：US20160181373A1

公开(公告)日：2016-06-23

申请号：US14908846

申请日：2014-06-13

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Takeyoshi Masuda ,  Taku Horii ,  Ryosuke Kubota

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/739 ,  H01L21/04 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/1608 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.

Abstract translation: 碳化硅半导体器件包括碳化硅层和栅极绝缘层。 碳化硅层具有主表面。 栅极绝缘层被布置为与碳化硅层的主表面接触。 碳化硅层包括具有第一导电类型的漂移区域，具有不同于第一导电类型并与漂移区域接触的第二导电类型的主体区域，具有第一导电类型并且布置成间隔开的源极区域 除了身体区域的漂移区域之外，还设置有从源极区域和漂移区域的至少一侧突出到体区的突出区域，与栅极绝缘层接触并具有第一导电型 。

公开(公告)号：US20160163545A1

公开(公告)日：2016-06-09

申请号：US14910169

申请日：2014-06-25

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Taku Horii ,  Takeyoshi Masuda

IPC: H01L21/02 ,  H01L29/16

CPC classification number: H01L21/02694 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/046 ,  H01L21/047 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.

Abstract translation: 碳化硅半导体衬底包括：具有外表面不小于100mm并由单晶碳化硅制成的主表面的基底; 形成在主表面上的外延层; 以及形成在与所述主表面相对的所述基底基板的背面上的变形抑制层。 以这种方式，变形抑制层抑制基板变形（例如，在高温处理期间翘曲）。 这可以降低在执行使用碳化硅半导体衬底的制造碳化硅半导体器件的方法时在制造过程中在碳化硅半导体衬底中产生诸如裂纹的缺陷的风险。

公开(公告)号：US09263527B2

公开(公告)日：2016-02-16

申请号：US14550402

申请日：2014-11-21

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Shunsuke Yamada ,  So Tanaka ,  Ryosuke Kubota ,  Taku Horii

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/306 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30604 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813

Abstract: A first impurity region is formed by ion implantation of a first impurity into a first main surface of a silicon carbide substrate. A metal layer is formed in contact with the first impurity region. By annealing the silicon carbide substrate and the metal layer, an electrode is formed. The metal layer is formed such that a concentration of a first impurity at a boundary portion between the metal layer and the first impurity region becomes less than a maximum value of a concentration of the first impurity in the first impurity region. The electrode is formed such that a concentration of the first impurity at a boundary portion between the electrode and the first impurity region becomes not less than 80% of a maximum value of a concentration of the first impurity in the first impurity region in a normal direction.

Abstract translation: 通过将第一杂质离子注入到碳化硅衬底的第一主表面中形成第一杂质区。 形成与第一杂质区接触的金属层。 通过退火碳化硅衬底和金属层，形成电极。 金属层形成为使得金属层和第一杂质区域之间的边界部分处的第一杂质的浓度变得小于第一杂质区域中的第一杂质的浓度的最大值。 电极形成为使得电极和第一杂质区域之间的边界部分处的第一杂质的浓度不小于在正常方向上的第一杂质区域中的第一杂质的浓度的最大值的80％ 。

公开(公告)号：US09741799B2

公开(公告)日：2017-08-22

申请号：US15023987

申请日：2014-08-05

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Toru Hiyoshi ,  Taku Horii ,  Takeyoshi Masuda ,  Shunsuke Yamada

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/16 ,  H01L21/28 ,  H01L21/04 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L21/049 ,  H01L21/28247 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode.

公开(公告)号：US09728607B2

公开(公告)日：2017-08-08

申请号：US14766955

申请日：2014-01-17

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Taku Horii ,  Masaki Kijima

IPC: H01L29/16 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L29/1608 ,  H01L21/02164 ,  H01L21/048 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/28 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/5329 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.

公开(公告)号：US09653297B2

公开(公告)日：2017-05-16

申请号：US15024260

申请日：2014-08-05

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Taku Horii ,  Tomoaki Ishida

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L21/22 ,  H01L21/02

CPC classification number: H01L21/046 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/045 ,  H01L21/0455 ,  H01L21/0465 ,  H01L21/049 ,  H01L21/22 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/739 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/872

Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the doped region at the first main surface, and a step of activating the impurity included in the doped region by annealing with the first protecting film having been formed, the step of forming a first protecting film including a step of disposing a material which will form the first protecting film and in which the concentration of a metal element is less than or equal to 5 μg/kg on the first main surface.

公开(公告)号：US09613809B2

公开(公告)日：2017-04-04

申请号：US14766963

申请日：2014-01-17

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Taku Horii ,  Masaki Kijima

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L21/033

CPC classification number: H01L21/0455 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/66068 ,  H01L29/7827

Abstract: A method of manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first mask layer is formed in contact with a first main surface of the silicon carbide substrate. The first mask layer includes a first layer disposed in contact with the first main surface, an etching stop layer disposed in contact with the first layer and made of a material different from that for the first layer, and a second layer disposed in contact with a surface of the etching stop layer opposite to the surface in contact with the first layer. A recess is formed in the first mask layer by etching the second layer and the etching stop layer. A first impurity region is formed in the silicon carbide substrate using the first mask layer with the recess. The first mask layer does not include a metallic element.

公开(公告)号：US09472635B2

公开(公告)日：2016-10-18

申请号：US14769472

申请日：2014-02-04

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Shunsuke Yamada ,  Taku Horii ,  Masaki Kijima

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/16 ,  H01L21/28 ,  H01L29/417 ,  H01L29/12 ,  H01L21/336

CPC classification number: H01L29/4941 ,  H01L21/0485 ,  H01L21/28 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/417 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a main electrode, a first barrier layer, and an interconnection layer. The main electrode is directly provided on the silicon carbide substrate. The first barrier layer is provided on the main electrode, and is made of a conductive material containing no aluminum. The interconnection layer is provided on the first barrier layer, is separated from the main electrode by the first barrier layer, and is made of a material containing aluminum.

Abstract translation: 碳化硅半导体器件包括碳化硅衬底，主电极，第一势垒层和互连层。 主电极直接设置在碳化硅衬底上。 第一阻挡层设置在主电极上，并且由不含铝的导电材料制成。 互连层设置在第一阻挡层上，通过第一阻挡层与主电极分离，并且由含铝的材料制成。