公开(公告)号：US20240339322A1

公开(公告)日：2024-10-10

申请号：US18564501

申请日：2022-04-26

Applicant: Hitachi Energy Ltd

Inventor： Giovanni ALFIERI ,  Lars KNOLL

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/73 ,  H01L29/739 ,  H01L29/868 ,  H01L29/872

CPC classification number: H01L21/047 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/73 ,  H01L29/7393 ,  H01L29/868 ,  H01L29/872

Abstract: The present disclosure relates to a semiconductor device (1) comprising at least one epitaxial layer (2) made from a first semiconductor material comprising carbon and having a [0001] crystallographic axis. At least one implantation area (4) is formed at a sidewall (3a) of the epitaxial layer (2), wherein a normal direction of the sidewall (3a) is perpendicular to the [0001] crystallographic axis. At least one part of the epitaxial layer (2) has a reduced concentration of carbon vacancy (VC) with respect to the first semiconductor material of the at least one epitaxial layer (2) as-grown. The present disclosure further relates to a method for manufacturing a semiconductor device (1), wherein ions are implanted through at least one sidewall (3a) of at least one epitaxial layer (2).

公开(公告)号：US20250006785A1

公开(公告)日：2025-01-02

申请号：US18290714

申请日：2022-06-09

Applicant: Hitachi Energy Ltd

Inventor： Gianpaolo ROMANO ,  Andrei MIHAILA ,  Marco BELLINI ,  Yulieth ARANGO ,  Lars KNOLL ,  Nazareno DONATO ,  Florin UDREA

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/739 ,  H01L29/78

Abstract: A power semiconductor device (10) comprises a semiconductor body (11) which includes a first main surface (12) and a second main surface (13), a gate insulator (14) arranged at the first main surface (12), and a gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) comprises a drift layer (16) of a first conductivity type, a well layer (27) of a second conductivity type being different from the first conductivity type and forming a first junction (18) to the drift layer (16), a source region (20) of the first conductivity type forming a second junction (21) to the well layer (27), and an island region (30) of the second conductivity type attaching the source region (20) such that the source region (20) separates the island region (30) from the well layer (27) in at least 50% of an island surface area of the island region (30) in the semiconductor body (11).

公开(公告)号：US20240222462A1

公开(公告)日：2024-07-04

申请号：US18554189

申请日：2022-03-25

Applicant: Hitachi Energy Ltd

Inventor： Vinoth SUNDARAMOORTHY ,  Lars KNOLL ,  Stephan WIRTHS

IPC: H01L29/45 ,  H01L21/04 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/7828

Abstract: The present disclosure relates to a method for forming an ohmic contact on a wide-bandgap semiconductor device comprising: shallow implanting a dopant through a first surface of a wide-bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region of a wide-bandgap semiconductor material, thermal treatment of the interface region comprising the implanted dopant at a temperature below 1100° C., and depositing a metal material on top of the at least one interface region to form at least one ohmic contact region.
The present disclosure further relates to a wide-bandgap semiconductor device comprising a semiconductor body or epitaxial layer comprising a wide-bandgap semiconductor material, at least one interface region which is doped and arranged within the wide-bandgap semiconductor material, and at least one ohmic contact region arranged on top of the at least one interface region.

公开(公告)号：US20240170566A1

公开(公告)日：2024-05-23

申请号：US18283169

申请日：2022-02-18

Applicant: HITACHI ENERGY LTD

Inventor： Andrei MIHAILA ,  Munaf RAHIMO ,  Lars KNOLL ,  Marco BELLINI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7802 ,  H01L29/0692 ,  H01L29/0856 ,  H01L29/1608 ,  H01L29/66712 ,  H01L29/7395

Abstract: A power semiconductor device (1) is provided, comprising



a drift layer (2) of a first conductivity type,
at least two well regions (3) of a second conductivity type being different from the first conductivity type, and
at least one intermediate region (4), wherein
the at least two well regions (3) and the at least one intermediate region (4) are provided within the drift layer (2) at a first side,
the at least one intermediate region (4) is provided between the at least two well regions (3), and
the at least one intermediate region (4) comprises at least one first doped region (5) of the first conductivity type and at least one second doped region (6) of the second conductivity type.

公开(公告)号：US20240413207A1

公开(公告)日：2024-12-12

申请号：US18694938

申请日：2022-09-27

Applicant: Hitachi Energy Ltd

Inventor： Giovanni ALFIERI ,  Lars KNOLL

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

Abstract: The present disclosure relates to a power semiconductor device (100) comprising a silicon carbide semiconductor. SiC. structure (110) comprising a SiC epilayer (112), at least one ohmic contact (120) formed on a first main surface (114) of the SiC structure (110), and at least Schottky barrier contact (130) formed on a second main surface (116) of the SiC structure (110). The at least one Schottky barrier contact (130) comprises a metal layer (136) and a carbon group interlayer (134) arranged between the metal layer (136) and the second main surface (116) of the SiC structure (110). 15 The present disclosure relates to a Schottky barrier diode (400). a vertical field effect transistor, such as a power MOSFET (500), and a method for manufacturing a power semiconductor device (100).